System For Generating Tracing Signals For Displaying Or Recording Characters

Abstract

In a display or recording device such as cathode ray tube or ink jet recording apparatus, the characters or indicia to be displayed or recorded are resolved into a plurality of strokes representative of X and Y components of the X-Y coordinate system to electrically store them in a memory. Then, the memory is interrogated to read out the information stored therein, and in accordance with the read-out information, control signals are generated to control the horizontal and vertical deflection electrodes to synthesize one stroke with another stroke for display or record of the characters or indicia. The strokes are classified into linear segments and arc segments. The arc segments which represent the curved portions of the characters are quantized into a plurality of steps and are formed by one of eight quadrant strokes by employing X and Y up-down counters. After the counters are set to an initial value representing the starting point of the arc segment, the X and Y counters are incremented in a plurality of steps each having values of 0,1, or 2 in either the up or down direction.

Description

The present invention relates generally to a character synthesizing system and more particularly to apparatus for generating tracing signals for displaying or recording characters or indicia.

With advent of electronic computers, the character recording and display devices are widely used as output equipment for providing the processed information in a form which can be readily and visually intelligible to a human being. The present invention may be advantageously applied to an ink jet recording device or a display device utilizing a CRT for electronically recording or displaying the characters or indicia (hereinafter referred to as "character" exclusively) upon a recording or display medium. In case of recording or displaying the characters by use of the ink jet recording device or the cathode-ray tube, a character is generally resolved into X and Y components and the sweep signals representative of the X and Y components are applied to the horizontal and vertical deflecting electrodes for recording or displaying the characters. In view of economy and reliability in operation, various digital control processes are employed in the character recording or display devices of the type described above. However, the characters are synthesized by the combinations of the linear segments when the character synthesizer is controlled digitally so that there is a defect that the synthesized character does not look natural, that is the character has edge ruggedness.

It is therefore the primary object of the present invention to provide an X and Y electrode control system capable of synthesizing a character consisting of linear segments and arc segments which represent the arcuated portions of the character with high fidelity under the control of a digital control circuit simple in construction.

Another object of the present invention is to provide a process and apparatus for generating the tracing signals for recording or displaying the characters having curved or arcuate portions two-dimensionally by use of memory means simple in construction.

Another object of the present invention is to provide a process and apparatus for generating tracing signals of the type in which the characters having curved or arcuate portions are resolved into X and Y components which in turn are divided into a plurality of strokes each of which is further quantized into a plurality of steps and which has memory means for storing therein the informations representative of the reference positions or initial values of the characters to be synthesized the information representative of the increase or decrease of one stoke relative to the preceding stroke, and the information representative of the increment or decrement in the quantized steps of one stroke.

Another object of the present invention is to provide a character synthesizing or tracing signal generating apparatus including memory means, X and Y up-down counter means operable in response to the informations representative of the increment or decrement and the information representative of a value of increment or decrement in a unit stroke, the X- and Y-counter means being set to the initial values in response to the information read out from the memory means and digital-to-analog converter means for converting the outputs from the counter means into the analog signals to be applied to the horizontal and vertical deflecting electrodes.

Another object of the present invention is to provide an improved tracing or display signal generating process and apparatus for resolving a two-dimensional character having curved or arcuate portions into the X and Y components of the X-Y coordinate system, quantizing each of said components into one or more unit steps, storing the information each representative of an initial value of an quantized component and the information representative of the increase or decrease of an quantized step relative to the preceding step and the information representative of a magnitude of the increment or decrement in each step, reading out the content of the memory in response to the display instruction and generating the output signals for synthesizing a two-dimensional character having a curved or arcuate portion in response to the read-out signal.

The present invention provides apparatus for synthesizing a character comprising resolving a character into X and Y components of the X-Y coordinate system, each of said X and Y components being composed of a plurality of unit strokes each having a predetermined unit length and making the increment or decrement of each of said components not equal, thereby forming a stroke of an arc portion, representing the stroke of the arc portion by a quadrant which is determined by a pattern composed of a plurality of dots, selecting the stroke of the arc portion by selecting one of a plurality of quadrants and synthesizing a character by combining the strokes of the arc portions with the other strokes. Therefore, the characters may be smoothly traced or synthesized under the control of the tracing or display signals.

The present invention provides apparatus for synthesizing the characters by resolving a character into X and Y components of the X-Y coordinate system, each of said X and Y components being composed of a plurality of unit strokes each having a predetermined unit length, storing information as to said unit strokes of said X and Y components into a memory and reading out from said memory the stored information for synthesizing the character. Strokes representative of an arc portion are divided divided into a plurality of steps. The apparatus includes means for reading from the memory the information representative of a reference position as an initial value into X and Y up-down counter means, setting said counter means to said initial value prior to the operation thereof, reading out from the memory means the information designating either of two patterns of the arc portions, simultaneously reading out from the memory means an information designating either of two operation modes in each step, and synthesizing the stroke of the arc portion with the other strokes, thereby generating the signals for synthesizing each of the characters. Therefore, the character synthesizing or tracing signals may be continuously generated.

Briefly, the apparatus of the present invention employs X and Y up-down counters each having up, down, and no-counting operation modes. Clock pulses of predetermined repetition rate are generated and connected to the counters to be counted. The digital outputs of the counters are converted by digital-to-analog converters to analog signals which are applied to the X and Y deflection means of the apparatus. Memory means is provided to store, as to each of the characters to be composed by a plurality of strokes each composed of a plurality of steps, the strokes including at least one quadrant stroke, information to be supplied to the counters for controlling the initial setting of the counters and for selecting one of the operation modes of the counters during a time period of each stroke. The memory means is connected to the counters for controlling the counters in accordance with the information supplied from the memory means, and means responsive to the information corresponding to the quadrant strokes generates control signals to shift the contents of the counters by predetermined values every step during the time period of the quadrant stroke. Access means in the form of a shift register supplies information to the counters every time period of each stroke, and means for selecting one of the characters to be composed is connected to the memory means. The clock pulses are connected to a ring counter for generating sequentially phase-shifted pulses during the time period of the quadrant stroke, the number of which is equal to the steps constituting the quadrant stroke, and the means responsive to the information corresponding to the quadrant strokes is connected to the sequentially phase-shifted pulses to produce the control signals supplied to the counters. The memory means is a matrix having two sets of control terminals one of which is connected to the selecting means and the other of which is connected to the access means.

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the illustrative preferred embodiment thereof with reference to the accompanying drawings in which:

FIGS. 1A, 1B and 1C are diagrams for explanation of synthesizing a character only by a combination of linear segments in accordance with the process proposed by the same inventor;

FIG. 2 shows a character having a curved or arcuate portions to be synthesized in accordance with the present invention;

FIG. 3 is for explanation of various types of arcs used in the present invention;

FIG. 4 shows the numerals synthesized by the combinations of the linear and arc segments in accordance with the present invention;

FIG. 5 is for explanation of the steps of programming the x-y coordinates of the dot patterns representative of the arcs used in synthesizing the numerals shown in FIG. 4;

FIG. 6 is a block diagram of one embodiment of character synthesizing apparatus in accordance with the present invention;

FIG. 7 is a circuit diagram of one embodiment of a memory identified by 600 in FIG. 6;

FIG. 8 is a circuit diagram of a selection circuit identified by 603 in FIG. 6;

FIG. 9 is a circuit diagram of a D-A converter and a reversible counter identified by 605 and 607 respectively in FIG. 6; and

FIGS. 10a-h show the relationship of various signals used in the instant embodiment of the invention.

Prior to the description the terms used in the specification are defined. The term "character" implies all indicia including alpha-numeric and symbols. The term "tracing signal" is a control signal for sweeping the electron beams or controlling ink jet to be ejected from a writting head for recording or display.

FIG. 1A illustrates one example of the character synthesized only by the linear segments and FIGS. 1B and 1C illustrate how the horizontal and vertical deflection potentials are quantized in order to synthesize the character illustrated in FIG. 1A. The horizontal deflection potential Vx is quantized into three discrete levels while the vertical deflection potential Vy is quantized into five discrete levels. These deflection potentials are applied to the horizontal and vertical deflecting electrodes of a cathode ray tube or an ink jet writing head for recording or display. The process and device based upon the principle described above are disclosed in applicant's copending U.S. Pat. Application Ser. No. 882057, filed Dec. 4, 1969, and the present invention will be described in conjunction with the above-mentioned process and device.

FIG. 2 illustrate one example of the character synthesized in accordance with the present invention and it is readily noted that the character looks more natural. The process and apparatus for synthesizing such character will be described in more detail hereinafter. First, the principle upon with is based the present invention will be discussed with the aid of the X-Y coordinate system.

FIG. 3 illustrates types of arc segments used for synthesizing the character in accordance with the present invention. There are illustrated eight arcs or quadrants starting from a starting point Po which is determined by the initial horizontal and vertical deflection potentials. They are the arc R.sub.1 and R.sub.2 starting from the point Po and terminating at the point Pa; R.sub.3 and R.sub.4 starting from point Po and terminating at the point Pb; R.sub.5 and R.sub.6 starting from the point Po and terminating at the point Pc; and R.sub.7 and R.sub.8 starting from the point Po and terminating at the point Pd. It is readily seen that the character which is synthesized by a combination of these arc segments and linear segments looks more natural than that synthesized only by the linear segments.

FIG. 4 illustrates the numerals synthesized by the various combinations of the arc and linear segments in accordance with the present invention and a reference or starting point at which the synthesize of a character is started is designated by a symbol O. It will be readily understood that a combination of the arc and linear segments for synthesizing a character will be determined by a character synthesizing matrix. The arc segments R.sub.1 -R.sub.8 used in synthesizing the numerals in FIG. 4 correspond to those illustrated in FIG. 3. When the arc segments R.sub.1 to R.sub.8 are traced from any suitably selected reference or starting point O, the objects of the present invention are accomplished.

It will be seen that each linear segment may be composed of a plurality of dots whose positions are functions of time and that for this purpose the horizontal and vertical deflection potentials being applied to the X and Y deflection electrodes may be controlled by the digital character generators under the control of the UP and DOWN instructions of the digital counters thereof. Each of the arc segments is also composed of a plurality of dots in accordance with the present invention.

FIG. 5 illustrates a dot pattern for synthesizing the arc segments represented in the X-Y coordinate system. As seen from FIG. 5, each arc segment is composed of eight dots which can represent the arc segment precisely and economically, but it will be understood that the number of dots composing an arc segment is not limited to eight. It is readily seen from FIG. 5 that a circle may be stroked or drawn first by drawing the arc segment r.sub.1 from the starting point Po, drawing the arc segment R.sub.3 continuously from the terminating point P.sub.7 and drawing the arc segments R.sub.5 and R.sub.7 in a similar manner.

Next with reference to FIG. 5 how the dots are determined so as to draw the arc segment will be described. Assume that the reference or initial point Po be already determined by X and Y deflection potential levels and the arc segment r.sub.1 be drawn. In the first step, the X deflection level remains unchanged while the Y deflection level is raised by two levels so that the point Do is displaced to P.sub.1. In the second step, the X deflection level is raised by one level while the Y deflection level is raised by two steps so that the point P.sub.1 is displaced to the point P.sub.2. In the third step, the X deflection level is raised by one level while the Y deflection level is raised by two levels so that the point P.sub.2 is displaced to the point P.sub.3. In a similar manner, the points are displaced from P.sub.3 to P.sub.4, from P.sub.4 to P.sub.5, from P.sub.5 to P.sub.6 and finally from P.sub.6 to P.sub.7. Thus, the arc segment R.sub.1 is traced. In a similar manner, all of the arc segments from R.sub.1 to R.sub.8 may b drawn as shown in Table 1.

TABLE 1 arc Segments II III IV VI VII (Step) _________________________________________________________________________ _ X 1 U 1 U 2 U 2 U 2 U r .sub.1 y 22 u 2 u 2 u 1 u 0 x 22 u 2 u 2 u 1 u 0 r .sub.2 y 1 u 1 u 2 u 2 u 2 u x 22 u 2 u 2 u 1 u 0 r .sub.3 y 1 d 1 d 2 d 2 d 2 d x 1 u 1 u 2 u 2 u 2 u r .sub.4 y 22 d 2 d 2 d 1 d 0 x 1 d 1 d 2 d 2 d 2 d r .sub.5 y 22 d 2 d 2 d 1 d 0 x 22 d 2 d 2 d 1 d 0 r .sub.6 y 1 d 1 d 2 d 2 d 2 d x 22 d 2 d 2 d 1 d 0 r .sub.7 y 1 u 1 u 2 u 2 u 2 u x 1 d 1 d 2 d 2 d 2 d r .sub.8 y 22 u 2 u 2 u 1 u 0 _________________________________________________________________________ _

FOOTNOTE: where U means that the level is raised. That is, 2 U means that the level is raised by two levels;

FOOTNOTE: D means that the level is decreased or down. That is, 2 D means that the level is decreased or down by two levels;

FOOTNOTE: 0 = the level remains unchanged or "inhibited;"

FOOTNOTE: X = X deflection potential level; and

FOOTNOTE: Y = Y deflection potential level.

Since the arc segments are curved in the same directions as will be readily seen from FIG. 3, Table 1 may be retabulated as shown in Table 2.

TABLE 2 Arc III II s IV V VI VII (Step) _________________________________________________________________________ _ 1 0 X.f 1 rw.U 2 2 2 2 r .sub.1 2 2 y.f2 arw.u 2 1 1 0 2 2 x.f2 arw.u 2 1 1 0 r .sub.2 1 0 y.f1 arw.u 2 2 2 2 2 2 x.f2 arw.u 2 1 1 0 r .sub.3 1 0 y.f1 arw.d 2 2 2 2 1 0 x.f1 arw.u 2 2 2 2 r .sub.4 2 2 y.f2 arw.d 2 1 1 0 1 0 x.f1 arw.d 2 2 2 2 r .sub.5 2 2 y.f2 arw.d 2 1 1 0 2 2 x.f2 arw.d 2 1 1 0 r .sub.6 1 0 y.f1 arw.d 2 2 2 2 2 2 x.f2 arw.d 2 1 1 0 r .sub.7 1 0 y.f1 arw.u 2 2 2 2 1 0 x.f1 arw.d 2 2 2 2 r .sub.8 2 2 y.f2 arw.u 2 1 1 0 _________________________________________________________________________ _

FOOTNOTE: where U means that X or Y deflection potential levels are increased or up continuously and sequentially; and

FOOTNOTE: D means that X or Y deflection potential levels are decreased or down continuously and sequentially.

From Table 2, it will be readily seen that except the fact that the potential levels are increased or up or decreased or down, the arc segments R.sub.1, R.sub.4, R.sub.5 and R.sub.8 are the same while R.sub.2, R.sub.3, R.sub.6 and R.sub.7 are the same inasmuch as the patterns or changes in level (0,1 and 2) in the sequential steps are concerned. Therefore, Table 2 may be also retabulated as shown in Table 3.

TABLE 3 First pattern I ep II III IV VII 1 0 hift 1 22 2 2 2 2 hift 2 21 1 0 Second pattern 2 2 hift 2 21 1 0 1 0 hift 1 22 2

From Table 3, it will be seen that in first pattern. the Y-shift is first large and becomes gradually smaller while the X-shift is first small and becomes gradually larger. In the second pattern, the X-shift is first larger and gradually becomes smaller while the Y-shift is first small and gradually becomes larger. The arc segments in the first pattern will be referred to as "Pattern A" while those in the second pattern will be referred to as "Pattern B". Then Table 3 may be retabulated as shown in Table 4.

TABLE 4 R.sub.1 Pattern A XU YU R.sub.2 Pattern B XU YU R.sub.3 Pattern B XU YD R.sub.4 Pattern A XU YD R.sub.5 Pattern A XD YD R.sub.6 Pattern B XD YD R.sub.7 Pattern B XD YU R.sub.8 Pattern A XD YU

from the foregoing, it will be seen that all of the eight arc segments may be drawn by designating the pattern whether the arc segments belong to Pattern A or Pattern B and the operation mode whether the X potential level is increased or decreased and the Y potential level is increased or decreased.

Next the apparatus for practising the present invention will be described. In order to change or shift the X and Y deflection potential levels in steps or discrete levels, digital counters are required. Each counter is a binary counter having a few bits, but it should be noted that it is capable of counting up and down not only by one step but also by two steps depending upon the instruction signals. By use of these counters of the type described, the control is much facilitated. These counters are similar in construction and are identified by 605 and 606 in the block diagram of FIG. 6. When the input signals are applied to both of the terminals U and I, the counter counts up by one; when the input signals are applied to the terminals U and II, the counter counts up by two; when the signals are applied to the terminals D and I, the counter counts down by one; and when the signals are applied to the terminals D and II, the counter counts down by two. Preset signals are applied to PS terminals of each counter. The counters 605 and 606 are connected to digital-to-analog converters D-A in order to convert the digital outputs derived from the counters 605 and 606 into the corresponding potential levels, thereby controlling the deflection potentials applied to the horizontal and vertical deflection electrodes 609 and 610 respectively.

The present invention will be further described with reference to the case of synthesizing one complete character shown in FIG. 4. FIG. 6 shows the block diagram of the overall device of the present invention. A pulse generator 601 generates the pulses having different phases .phi.1 and .phi.2 as shown in FIG. 10 (a ). By the clock pulses generated by the pulse generator 601, a ring counter 602 is driven so as to generate the output pulses as shown in FIG. 10 (b ) - (d ). The pulses S1 shown in FIG. 10 (b ) are applied to a shift register 604 so that it generates the output pulses as shown in FIG. 10 (e ) - (g ). The pulses S1 - S7 are applied to a selection circuit 603 so that one-step-count or two-step-count instruction signals are applied to the terminals I or II of the counters 605 and 606 depending upon the instruction representative of Pattern A or Pattern B derived from a programmed memory 600. The memory 600 comprising diodes or transistors (See FIG. 7) presets the reversible counters 605 and 606 when the timing pulse t.sub.1 is derived from the shift register 604 and when the input signal as shown in FIG. 10 (h ) is applied to one of the recording or display terminals 0 - n. Therefore, the reversible counters 605 and 606 are operated as described hereinabove so that the outputs of the counters are converted by D-A converters 607 and 608 and the corresponding deflection potentials are applied to the horizontal and vertical deflection electrodes 609 and 610.

FIG. 7 is a detailed circuit diagram of the memory 600 to which are connected the exterior or peripheral circuits 603, 605 and 606. The memory 600 is shown as being programmed for synthesizing the numeral 5 shown in FIG. 2. I.sub.1 and I.sub.2 are inverters; 01 through 06, OR gates; Do through D8 diodes; and R.sub.0 through R.sub.8 resistors. They are wired as shown. The selection circuit shown in FIG. 8 comprises AND gates AND-1 through AND-8 and OR gates OR-1 through OR-8 and controls the counters 605 and 606 in shifting the contents thereof. 602 is a ring counter for generating 7-step sequential time control signals. When the arc segment of Pattern A is selected, the shift-steps of the X and Y deflection potential levels are determined based upon First Pattern in Table 3. The selection circuit will be readily understood when taken in conjunction of First Pattern in Table 3. Since output "1" is derived from the terminal A, in the step I (S-I) the signal passes through the OR gate OR-1, AND gate AND 1 and OR gate OR-5 and is applied to the terminal II of the counter 606 so that the counter 606 is shifted by two steps. In this case, a signal is sent from the memory 600 to the terminal U, the counter is UP while when signal is applied to the terminal D, the counter is DOWN. Since no signal is applied to the terminals I and II of the reversible counter 605, it remains unchanged. In the second step II (S-II), the signal passes through the OR-1, AND-1, and OR-5 so that Y-counter is shifted by two steps and simultaneously the signal passes through OR-3, AND-6 and OR-8 so that X-counter is shifted by one step. In the third step S-III, the signal is applied through OR-1 so that Y-counter is shifted by two steps while the signal is simultaneously applied through OR-1 so that X-counter is shifted by one step. In the fourth step S-IV the signal is applied through OR-1 so that the Y-counter is shifted by two steps while the signal is simultaneously applied through OR-2 so that X-counter is shifted by two steps. In S-V, the signal passes through OR-2 and OR-4. The signal is applied through OR-2, AND-4 and OR-6 so that X-counter is shifted by two steps. Simultaneously, the signal is applied through OR-4, AND-7 and OR-7 so hat the Y-counter is shifted by one step. In S-VI, the signals passes through OR-2 and OR-4 so that the X-counter is shifted by two steps while the Y-counter is shifted by one step. In S-VII the signal is applied through OR-2, AND-4 and OR-6 so that only the X-counter is shifted by two steps.

From the foregoing it will be seen that when the terminal A is "1", the shift for tracing the arc segment of the First Pattern in Table 3 may be accomplished. The arc segment of Second Pattern in Table 3 is synthesized when the signal "1" is applied to the terminal B in the circuit of FIG. 8. As seen from FIG. 8, in S-I, only X-counter is shifted by two steps; in S-II and S-III, X-counter is shifted by two steps while Y-counter is shifted by one step; in S-IV, both of X- and Y-counters are shifted by two steps; in S-V and S-VI, the X-counter is shifted by one step while Y-counter is shifted by two steps; and in S-VII, only Y-counter is shifted by two steps. Thus, the shift for tracing the arc segment of Second Pattern in Table 3 is accomplished. From the foregoing description in conjunction with FIG. 8 it is now clear that all of the arc segments shown in Table 4 are traced. In short, in order to trace the arc segments from R.sub.1 to R.sub.8 the conditions shown in Table 4 are applied as control signals to the circuit of FIG. 8.

FIG. 9 is a circuit diagram of the reversible counter 605 and the D-A converter 607. In the counter 605, FF-1 to FF-n are J.K. flip-flops; AU-1 to AU-n are AND gates which are selectively opened in response to UP instructions; AD-1 to AD-n are AND gates which are selectively opened in response to DOWN instructions; Oi-1, Oi-2 and Oi-3 are input OR gates; and A1 is an input AND gate.

The mode of operation of the reversible counter is as follows: When the UP instruction is applied to the UP terminal while the display signal is applied to the terminal I, AND gate A1 is opened so that the input signal "1" is applied to the input terminals J and K of the flip-flop FF-1. The flip-flop FF-1 reads in response to the clock pulses .phi..sub.1 and generates the output in response to the clock pulses .phi.hd`and then reverse into the state of .theta. = 1 and .theta. = 0. When the UP instruction remains applied while the display signal is applied to the terminal II, AND gate AU-1 is opened so that the signal "1" is applied to the input terminals J and K of the flip-flop FF-2. In response to the clock pulses the flip-flop FF-2 are reversed into the state of .theta. = 1 and .theta. = 0. The outputs from the flip-flops FF-1 and FF-2 are applied to the D-A converter 607 so that an output corresponding to the input is derived from the terminal X-out. When the instruction is changed from UP to DOWN while the signal is applied to the terminal I, AND gate Ai is opened while the flip-flop FF-1 is reversed into the state of .theta. = 0 and .theta. = 1. Since the DOWN signal is applied to the gate AD-1 when .theta. = 0, it remains closed so that no input is applied to the flip-flop FF-2, that is the flip-flop FF-2 remains unchanged. From the foregoing, it will be seen that the reversible counter can accomplish not only one-step UP and DOWN but also two-step UP and DOWN and is very effective for carrying out the present invention. The reversible counter 606 has the same construction and function as the counter 605.

The outputs from the reversible counter 605 are applied to the stages of the D-A converter 607 which is composed of a ladder circuit of the type well known in the art so that a detailed description will not be made. The output from the terminal X-out of the D-A converter 607 is applied to the horizontal deflection electrode 609. The output of the reversible counter 606 is applied to the D-A converter 608 and the output of the D-A converter 608 is applied from the terminal Y-out to the vertical deflection electrode 610.

Next the mode of operation of the circuits described in detail hereinabove will be described with reference to the case when the numeral "5" shown in FIG. 2 or FIG. 4 is traced or synthesized. In the strokes (1) - (5) and (8), the linear segments are used so that the process disclosed in the copending U.S. Pat. Application Ser. No. 882057 may be employed for tracing these segments. In the strokes (6) and (7), the arc segments R.sub.3 and R.sub.5 are employed. The circuits in the illustrated embodiment are constructed based upon the negative logic for the sake of convenience. To the terminal 5 of the circuit illustrated in FIG. 7 is applied the input signal (for example the signal shown in FIG. 10 (h)) and the input signal (for example as shown in FIG. 10 (e)) is applied from the shift register 604 to the output terminal t.sub.1, the signal is derived from the junction Po between the diode Do and the resistor Ro at the crosspoint of the wire extending from the terminal 5 with the wire extending from the terminal t.sub.1. The signal is applied to the terminal INH of the reversible counter 605 through the OR gate O.sub.1 and the inverter I.sub.1. Therefore the operation of the counter 605 is "inhibited". Simultaneously, the signal from the junction Po is applied to the preset terminal 2 of the reversible counter 605 so that it is set to "14" in the instant embodiment in which one stroke in the time interval T.sub.1 consists of seven unit steps because the reference point (or coordinate) is X = 2 and Y = 4. The signal is applied to the preset terminal 4 of the reversible counter 606 so that it is set to "28". The signal is also applied to the INH terminal through the OR gate O.sub.3 and the inverter I.sub.2 so that the reversible counter 606 will not initiate to count even when the clock pulses are applied thereto as is the case of the reversible counter 605.

When the signal applied to the terminal t.sub.1 is ceased while the signal is applied to the terminal t.sub.2, the signal is derived from the junction P.sub.1 between the diode D.sub.1 and the resistor R.sub.1 at the second crosspoint and is applied to the DOWN terminal D of the reversible counter 605 so that the counter 605 functions as a DOWN counter. Therefore, 7 counts are subtracted during the T.sub.2 period and the counter is finally set to "7". The signal from the junction P.sub.1 is also applied to the INH gate of the reversible counter 606 so that its content remains unchanged. The output pulses from the shift register are applied to the terminals t.sub.3 , t.sub.4, t.sub.5, t.sub.6 and so on sequentially so that both of the reversible counters 605 and 606 are operated in accordance with the content of the programmed memory.

Therefore, the outputs from the counters 605 and 606 are converted into the horizontal and vertical deflection potentials by the D-A converters, which are applied to the horizontal and vertical deflection electrodes 609 and 610 respectively thereby synthesizing the character for recording or display. No further description will be made because the mode of operation is described in detail in the copending U.S. Pat. Application Ser. No. 882057. However, the present invention will be described in detail from the sixth step when the signal is applied to the terminal t.sub.6 from the shift register.

Upon application of the signal to the terminal t.sub.6, the signal is derived from the junction P.sub.6 between the diode D.sub.6 and the resistor R.sub.6 and is applied through the OR gate O.sub.5 to the UP terminal U of the reversible counter 605. The signal is also applied to the DOWN terminal D of the reversible counter 606 through the OR gate O.sub.2. The signal representative of Pattern B arc segment is applied to the terminal B of the selection circuit 603 from the memory 600. Referring to FIG. 8, when Pattern B is specified, the counter 605 operates as an UP counter and the counter 606 operates as a DOWN counter. Thus, arc segment R.sub.3 as shown in FIG. 5 is traced. More specifically, the reversible counter 605 as shown in FIG. 9, which has been set to "7" in the fifth stroke (5), counts up by two in accordance with the first clock pulse with phases .phi..sub.1 and .phi..sub.2. This counter 605 counts up two by two in response to the second, third, and fourth clock pulses. Then, since the terminal I is specified, the counter 605 counts up one by one in response to the fifth and sixth clock pulses. The seventh clock pulse cannot operate the reversible counter 605 because no input appears on the terminal INH and the AND gate A1 is inhibited. Therefore upon accomplishment of the 6th stroke, that is at the time the pulse T.sub.7 applied to the terminal t.sub.7 is disappeared, the reversible counter 605 is set to "17" = "7" + "10".

On the other hand, the reversible counter 606, which has been set to "14" in the preceding stroke S(5), does not operate in response to the first clock pulse because no input appears on the terminal INH and the AND gate Ai is inhibited. Since the terminal I is then specified in the second and third clock pulses, the counter 606 counts up one by one. Thereafter, the counter 606 counts up two by two in response to the fourth, fifth, sixth and seventh clock pulses, since the terminal II is specified, that is, the signal is applied to the terminal II. Therefore, when the 6th stroke is accomplished, the reversible counter 606 is set to "24" = "14" + "10". These signals are applied to the D-A converters 607 and 608 so that the horizontal and vertical deflection potentials are generated and applied to the deflection electrodes 609 and 610, whereby the arc segment R.sub.3 shown in FIG. 3 may be traced for recording or display.

From the foregoing, it will be readily seen how the arc segment R.sub.5 may be traced. The linear segment in the 8 - 9 stroke may be traced in a manner as disclosed in the above-mentioned copending U.S. Pat. Application Ser. No. 882057.

On the other hand, the reversible counter 606, which has been set to "14" in the preceding stroke S(5), does not operate in response to the first clock pulse because no input appears on the terminal INH and the AND gate Ai is inhibited. Since the terminal I is then specified in the second and third clock pulses, the counter 606 counts up one by one. Thereafter, the counter 606 counts up two by two in response to the fourth, fifth, sixth and seventh clock pulses, since the terminal II is specified, that is, the signal is applied to the terminal II. Therefore, when the 6th stroke is accomplished, the reversible counter 606 is set to "24" = "14" + "10". These signals are applied to the D-A converters 607 and 608 so that the horizontal and vertical deflection potentials are generated and applied to the deflection electrodes 609 and 610, whereby the arc segment R.sub.3 shown in FIG. 3 may be traced for recording or display.

From the foregoing, it will be readily seen how the arc segment R.sub.5 may be traced. The linear segment in the 8 - 9 stroke may be traced in a manner as disclosed in the above-mentioned copending U.S. Pat. Application Ser. No. 882057.

Claims

1. In character synthesizing apparatus of the type including a clock pulse generator supplying pulses of a predetermined rate, X and Y up-down counters coupled to said clock pulse generator for counting only said clock pulses, means for selectively causing said counters to count up or count down by discrete increments or decrements, or not count, in accordance with portions of a character to be depicted in straight line form, X and Y digital-to-analog converts to convert the outputs of said counters to analog signals, and X-Y tracing means driven by said analog signals, the improvement for providing curved character strokes comprising: means for selectively modifying the operation of at least one of said counters by selectively causing said at least one counter to be incremented or decremented by increments or decrements differing from said discrete increments or decrements in response to each of said clock pulses during a time interval assigned for the production of a curved line stroke, whereby the altered response of the counter due to said selective

2. The apparatus as recited in claim 1, wherein said means for modifying the operation of said at least one counter includes means for progressively modifying the operation of the counter during successive segments of a stroke for producing a curve composed of said segments, whereby strokes of any desired configuration may be formed without

3. The apparatus as recited in claim 1, wherein said means for modifying the operation of said at least one counter includes means for simultaneously activating a group of counting elements in said at least one counter such that each element in said group changes state upon the receipt of a clock pulse, and means for summing the outputs of the elements in said group for increasing the number represented by the output of said at least one counter in proportion to the number of said elements

4. The apparatus as recited in claim 1, wherein each of said characters is generated by a combination of straight and curved strokes, wherein said curved strokes comprise eight arcs each formed by seven sequential steps and wherein the counter operation modifying means increments or decrements the counters for executing a curved stroke in one or a sequence of the following progressions:

Are Segments I II III IV V VI VII (Step) _________________________________________________________________________ _ 0 X.f1 arw.U 1 2 2 2 2

A 2 X.f2 arw.U 2 2 1 1 0 2 X.2wdarw.U 2 2 1 1 0

B 0 X.f1 arw.U 1 2 2 2 2 2 X.f2 arw.U 2 2 1 1 0

C 0 X.f1 arw.D 1 2 2 2 2 0 X.f1 arw.D 1 2 2 2 2 0 X.f1 arw.U 1 2 2 2 2

D 2 X.f2 arw.D 2 2 1 1 0 0 X.1wdarw.D 1 2 2 2 2

E 2 Y.2wdarw.D 2 2 1 1 0 2 X.2wdarw.D 2 2 1 1 0

F 0 Y.1wdarw.D 1 2 2 2 2 2 X.2wdarw.D 2 2 1 1 0

G 0 Y.1wdarw.U 1 2 2 2 2 0 X.1wdarw.D 1 2 2 2 2

H 2 Y.2wdarw.U 2 2 1 1 0 _________________________________________________________________________ _ where U means that the X or Y analog signal levels are increased and where D means that the X or Y analog signal levels are decreased in accordance with the numbers in said table and where the numbers in said table refer to the amount that the indicated counter is incremented or decremented in response to an incoming clock pulse.