Waveform and symbol display system

Abstract

A system for displaying visual images of a signal containing data or information and of a symbol or alphanumeric character indicative of a characteristic of the signal. The system includes, in combination with a display of the cathode ray tube type, means for applying to the display a composite vertical deflection signal which alternately traces the vertical components of the data signal and the symbol categorizing the signal. The system further includes means for applying to the display a composite horizontal deflection signal which alternately traces the horizontal components of the data signal and the symbol. The system also includes means for applying to the display blanking signals to form a visual image of the symbol. Visual images of the data signal and the symbol are produced simultaneously on the display in spaced, corresponding relation and the system is capable of holding the images on the display for prolonged viewing.

Description

BACKGROUND OF THE INVENTION

This invention relates to the analysis of information signals, and more particularly to a new and improved system for displaying and analyzing signals containing information.

One area of use of the present invention is in monitoring physiological signals derived from electrocardiographic and other measurements although the principles of the invention can be applied to the observation and study of other information containing signals. These signals can be displayed upon oscillographic displays in which the signal moves across the screen from one edge to the other. In recent times a non-fading or refreshed cathode ray tube display has been developed which has the capability to show non-recurrent, low frequency signals for extended periods of time thereby greatly improving the visual analysis of data.

Visual analysis of information signals could be significantly improved by a system of displaying visual images of the signal and a symbol bearing a relation to the signal. In particular, it would be highly desirable to provide a system for displaying a visual image of a signal containing information or data and a visual image of a selected symbol or alphanumeric character indicative of the nature or characteristics of the signal. Such a system also should have the capability of displaying the signal and symbol for extended periods of time.

SUMMARY OF THE INVENTION

It is, therefore, an object of this invention to provide a new and improved display system for visual analysis of information signals.

It is a more particular object of this invention to provide a system for displaying visual images of a signal containing data or information and of a symbol or alphanumeric character selected according to the nature of the signal.

It is a further object of this invention to provide such a display system capable of displaying the signal and symbol for extended periods of time.

The present invention provides a system for displaying a visual image of a signal containing data or information and a visual image of a selected symbol or a alphanumeric character indicative of the nature or characteristics of the signal. The system includes a display means of the type having display trace sweeps and means for applying to the display means a composite signal which alternately traces the vertical components of the data signal and the symbol, a composite signal which alternately traces the horizontal components of the data signal and the symbol, and blanking signals which form a visual image of the symbol. Visual images of the data signal and the symbol are produced simultaneously on the display in spaced, corresponding relation and the system preferably provides a display of the refreshed or non-fading type.

The foregoing and additional advantages and characterizing features of the present invention will become clearly apparent upon a reading of the ensuing detailed description together with the included drawing wherein:

BRIEF DESCRIPTION OF THE DRAWING FIGURES

FIG. 1 is a system block diagram of apparatus according to the present invention;

FIG. 2 is a schematic block diagram of the portion of the system of FIG. 1 which provides a composite vertical signal;

FIG. 3 is a schematic block diagram of the portion of the system of FIG. 1 which provides a composite horizontal signal;

FIGS. 4 and 5 are schematic block diagrams which together illustrate the portion of the system of FIG. 1 which provides blanking signals;

FIG. 6 is a schematic block diagram of the portion of the system of FIG. 1 which generates timing signals;

FIG. 7 is a schematic block diagram of the portion of the system of FIG. 1 which generates command signals;

FIG. 8 is a graph of waveform illustrating the operation of certain portions of the system of the present invention; and

FIG. 9 is a graph of waveforms illustrating the operation of other portions of the system of the present invention.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

FIG. 1 is a block diagram of the system of the present invention in combination with display means 10 of the type having a display trace sweep for providing a visual image in response to signals applied thereto. Display means 10 is of the cathode ray tube type which operates in response to vertical deflection, horizontal deflection and blanking signals in a manner well understood by those skilled in the art. The system of the present invention comprises means for providing a signal representing information or data which is to be viewed or analyzed visually on display means 10. The system of the present invention further comprises means for providing a signal representation of a symbol or alphanumeric character selected according to the nature or characteristics of the information signal. In accordance with the present invention, the information signal and the signal representation of the symbol or character are applied to display means 10 for providing visual images of the information signal and the symbol or character simultaneously on display means 10 in spaced corresponding relation to each other.

In the system of FIG. 1, an analog signal which varies in accordance with data or information is available on line 16 and is applied to the input of an amplifier 18. One type of analog signal contemplated to be processed by the system of the present invention is a physiological signal, obtained from electrocardiographic or other physiological monitoring, which is a relatively low frequency, non-recurrent signal. The system of the present invention is contemplated for use in the visual analysis of other analog signals derived from measuring or monitoring other physical and chemical phenomena. For processing physiological signals and other analog signals in the same or higher frequency range, the system of the present invention includes means for providing a display of the non-fading or refreshed type. The amplified analog signals are applied to the input of an analog to digital converter 20 which samples the signal periodically and generates digital words signifying the instantaneous amplitude of the analog signal at the time of sampling. Typically the digital words are eight bits in length, each word representing a different code, and various codes are assigned to a particular value of the input signal range whereby the analog voltage can be described at any instant by one of a number of possible codes or digital words. The digital words from converter 20 are applied to the input of a delay memory system or loop 22 wherein they are shifted through the memory and then recirculated a predetermined number of times whereupon the words are applied to a video or display memory system or loop 24 wherein they are also shifted and recirculated for a predetermined number of times. The construction and operation of memory systems 22, 24 will be described in detail presently. The digital words from memory system 24 are applied to the input of a digital to analog converter 26 which converts the codes to analog signals in accordance with the code word values which were determined by analog to digital converter 20. The analog signals provided by converter 20 are connected by a line 27 to one input of a multiplexing means 28 for applying these analog signals to display means 10 to form a visual image thereof. Means 28 also applies to display means 10 signals for forming an image of a symbol or alphanumeric character representative of the nature of characteristics of the analog signal and these signals applied by means 28 are provided by the system of the present invention in a manner which now will be described.

The input analog signal present on line 16, for example a physiological signal, also is connected by a line 29 to the input of a computer means 30 which functions to examine the analog signal, place the signal in one of a predetermined number of categories depending upon nature or characteristics thereof, and provide a digital output signal coded in terms of the category. According to a preferred mode of the present invention, computer means 30 is programmed to place the analog signal in one of a maximum of eight categories thereby providing a three bit digital output signal. The digital code signal from computer means 30 is synchronized by means 32 with the rest of the system in a manner which will be described, and is applied to the input of a character memory loop or system 34 wherein each word is shifted and recirculated a predetermined number of times in a manner similar to that of memory means 24. Each digital word at the output of memory 34 is applied to the input of a character generator means 36 wherein the three bit digital word or code is converted into signals which, in turn, are processed and applied to display means 10 for generating an image of a symbol or alphanumeric character corresponding to that particular digital word or code.

The signals from character generator 36 are first applied by line 37 to an input of multiplexing means 2 wherein they are arranged or synchronized with the analog signal on line 27 so that visual images of the analog signal and the symbol appear simultaneously on display means 10 in spaced, corresponding relation. The system of the present invention further comprises clock and control circuit generally designated 40 in FIG. 1 which provides timing and control signals for operating the various components of the system in a manner which will be described in detail presently.

Accordingly, in response to an analog signal applied to the input of the system of the present invention, the following signals are applied to the display means 10 which is of the cathode ray tube type. A composite vertical deflection signal on line 42 alternately traces the vertical components of the analog information or data signal and the symbol or alphanumeric character which categorizes the analog signal. On line 44 there is a composite horizontal deflection signal which alternately traces the horizontal components of the analog signal and the symbol or character. Finally, on line 46 there are blanking signals for forming a visual image of the symbol or character on the screen of display means 10.

FIG. 2 illustrates in further detail the portion of the apparatus of the present invention which generates the composite vertical deflection signal present on line 42 of FIG. 1. Analog to digital converter 20 is operated to sample the analog signal applied thereto at a rate controlled by the frequency or repetition rate of A/D control timing pulses generated in another portion of the system which will be described. According to a preferred mode of the present invention, converter 20 is operated at a sampling rate of at least three times and preferably about four times the highest analog frequency to be produced. Line 50 in FIG. 2 is a path collectively representing eight lines from the output of converter 20 each line being provided for one of the eight bits in the digital words. The eight lines of path 50 are applied to a flip-flop means 52 which functions as a latching means for temporary data storage. The operation of flip-flop means 52 is controlled by a Store Control signal present on a line 53 which is generated in a manner which will be described. Typically, flip-flop means 52 comprises two quadruple flip-flop elements, one for each four of the eight bits of the input, and the Store Control signal on line 53 is applied simultaneously to the two flip-flips. The output of flip-flop means 52 is connected by a path 54 having eight lines for the eight bit output, to a set of eight inputs of a digital switching means 56. The eight bit output of digital switch 56 is connected by an eight line path 58 to corresponding inputs of a shift register means 60. After a predetermined time shift register means 60 transmits each eight bit word through a path 62 to the input of video or display memory systems 24. The eight bit output of register means 60 also is connected by an eight line path 64 to a second set of inputs of digital switching means 56.

Digital switching means 56 is controlled by a Read signal present on line 66 annd generated in a manner which presently will be described. In typical form, digital switching means 56 comprises two switching elements one of which controls four outputs of flip-flop means 52 and four outputs of register means 60 and the other of which controls the remaining four outputs of flip-flop 52 and of register 60. In this case, the true and complement values of the Read signal provided by the arrangement of Nor gates 67 and 68 shown in FIG. 2 are applied simultaneously to control inputs of both of the two switch components in a manner readily apparent to those skilled in the art. The circle present at the output of gates 67 and 68 means that the signal produced is relatively negative when it represents the bit one. A Delay Dump control signal present on line 69 is applied also simultaneously to gates 67 and 68 and is generated under certain conditions which will be described further on in the specification. Shift register means 60 typically comprises four separate dynamic shift register devices each having two shift registers with two inputs and two outputs and controlled by clock pulses present on line 70 which is connected to an input of each register element in a manner readily familiar to those skilled in the art.

Memory means 22 operates in the following manner. Digital words progress sequentially through shift register means 60 and then are recirculated once for every two digital words that are inserted into the shift register means 60. In dynamic shift registers the power consumption is proportional to the rate of shifting, and in the system according to the present invention wherein the registers are circulated once for every two words applied to the inputs thereof, the bandwidth requirements are kept low. The flicker rate requirements of display means 10 will govern the lower limit for the memory recirculation speed. Digital switching means 56 connects the input of register means 60 to either the output of flip-flop means 52 or to path 64 from the output of register means 60 under control of Read signals present on line 66. The system timing is designed to provide the following sequence of events. The first word from analog to digital converter 20 on path 50 is held in flip-flop 52 and while this word is temporarily stored in flip-flop 52 the next word will be present at the output of converter 20 which itself serves as a temporary storage element. Then the Store Control signal appears on line 53 and the Read signal appears on line 56 to cause flip-flop means 52 to transmit the two words together to digital switching means 56 which, in turn, directly applies these two words sequentially to the input of shift register means 60. These two words progress sequentially through the registers 60 under control of the clock pulses on line 70. When the Store Control signal disappears, flip-flop means 52 returns to the state for temporary storage of the next word from converter 20, and at the same time switch 56 operates to connect the word from path 64 to the input of shift register means 60. Thus every two words applied to the input of shift register means 60 two words from the output are recirculated back to the input thereof. According to a preferred mode of the present invention, register means 60 has a capacity of 512 words and provides a time delay of about 2.56 seconds. In other words, each digital word remains in memory means 22 for a period of about 2.56 seconds. Each time shift register means 60 is updated the digital word at the output of register means 60 means 60 also is applied to the input of memory means 24. Memory means 24 includes digital switching means 72 which is similar in construction and operation to digital switching means 56 and likewise typically includes two separate switching elements. The eight bit output of switching means 72 is applied by a path 74 to the input of a shift register means 76. The eight bit output of shift register means 76 is connected by a path 78 to the input of digital to analog converter 26. The output of register means 76 also is applied by a path 80 to another set of inputs of switching means 72. Shift register means 76 is controlled by memory clock pulses present on line 82 and generated in a manner which presently will be described. Digital switching means 72 is controlled by the same Read signal present on line 66 which controls switching means 56. An identical arrangement of NOR gates 83, 84 is provided and connected to the two elements comprising digital switching means 72 in a manner identical to that of switching means 56. A Video Dump signal present on line 86 is applied simultaneously to gates 83, 84 for the same purpose as the Delay Dump signal present on line 59. The outputs of gates 83, 84 are connected by lines 87 and 88, respectively, to another portion of the apparatus wherein they perform similar control functions.

Digital words are applied to the input of memory means 24 only when shift register means 60 of memory means 22 is updated. Thus memory means 22 provides a holding or temporary storage action for memory means 24 so that no latch element is needed in the latter. Words from shift register means 60 are transmitted under control of switch 72 into shift register means 76 wherein they progress sequentially under control of the clock pulses on line 82. After two words are inserted into register 76, switch 72 operates to connect the word from path 80 to the input of shift register means 76. In preferred form shift register means 76 comprises eight separate memory elements each having one input and one output. Line 82 is connected to an input of each memory element for applying clock pulses in a manner similar to the connection of line 70 to the elements of register means 60. Shift register means 76 has a capacity of 1,024 words and a delay of about 5.12 seconds whereby each digital word remains therein for a period of about 5.12 seconds.

The digital words or codes present on line 78 are converted to corresponding analog signals by converter 26 in accordance with the code word values determined by converter 20, which signals then are filtered to remove the digitizing step portions by a filter means 90, the output of which is applied to the input of a buffer amplifier 92. The output of amplifier 92 is connected by a line 94 to a potentiometer 96 for adjusting the amplitude of the signal. The signal present on the wiper arm 97 of potentiometer 96 could be applied directly to the vertical deflection terminal of a cathode ray tube oscilloscope for providing the vertical deflection component of a refreshed analog signal display. According to the present invention, however, the signal is correlated with the vertical deflection component of a signal for generating a symbol or alphanumeric character in the following manner.

The signal present on line 97 is applied to a first voltage controlled switching means 98 which is operated to connect and disconnect the signal line 97 into the vertical deflection circuit at a predetermined rate. Control of switching means 98 is provided by a multiplexing or switching signal present on line 100 and generated in a manner which will be described. The multiplexing signal on line 100 is applied through a resistor 101 to the base terminal of a transistor switch 102, the emitter terminal of which is grounded. The collector terminal of transistor 102 is connected through a resistor 103 to the base terminal of a transistor switch 104, the emitter terminal of which also is grounded. The collector terminal of transistor 104 is connected by a line 105 to the control terminal of voltage controlled switching means 98. The signal present on line 106 is a step waveform or staircase type signal providing the vertical deflection component of the signal for generating a symbol or alphanumeric character image on display 10. This signal is generated in a manner which presently will be described. Line 106 is applied to one input of an amplifier 107, the other input of which is connected through a resistor 108 to ground. The output of amplifier 107 is connected to a potentiometer 109, the wiper arm of which is connected by a line 110 to a second voltage controlled switching means 112. Potentiometer 109 adjusts the magnitude of this component of the vertical deflection signal and therefore the height of the character or symbol which will appear on the screen of display 10. The control terminal of switching means 112 is connected by a line 113 to the collector terminal of transistor 102. The outputs of switching means 98 and 112 are connected together by lines 115 and 116 which are connected through a resistor 117 and a line 118 to one input of an amplifier 119. Line 118 is connnected through a resistor 120 to the wiper arm of a potentiometer 121, one terminal of which is grounded and the other terminal of which is connected by a line 122 to line 100 on which the multiplexing signal is present. By virtue of this arrangement, the multiplexing signal is scaled down by the adjustment of potentiometer 121 to control the spacing between the vertical components of the analog signal and the symbol or character signal. The other input of amplifier 119 is connected through a resistor 124 to the wiper arm of the potentiometer 126 connected between positive and negative equal magnitude bias voltages for controlling the vertical position of the entire image on the screen of display 10. The output of amplifier 119 is connected through a resistance-capacitance network to line 42.

The multiplexing signal on line 100 is a square wave or on-off dc type signal which alternates or switches at a predetermined, constant rate. The arrangement of transistors 102 and 104 is such that when the multiplexing signal is on or at a relatively high magnitude switching means 112 is off or open and switching 98 is operated to connect the analog component of the vertical deflection signal through the circuit to line 42. When the multiplexing signal switches off or to a relatively lower magnitude, switching means 98 is off and switching means 112 is turned on or closed to connect the symbol or character component of the vertical signal through the circuit to line 42. As a result, the vertical step of deflection signal on line 42 alternates between the analog component and the symbol or character component during each sweep as will be described in further detail presently. Accordingly to a preferred mode of the present invention, the multiplexing signal switches one hundred times per second, i.e., switches to the high level fifty times and switches to the low level fifty times each second, thereby providing fifty vertical traces or sweeps of the analog signal and another fifty vertical traces or sweeps of the symbol or character during each second of time.

FIG. 3 shows in detail a portion of the apparatus of the present invention for providing the composite horizontal deflection signal on line 44 of FIG. 1. In the system of the present invention, as a matter of design choice, a logical one is represented by plus 5 volts, a logical zero by zero volts, and most bias voltages have a magnitude of about 15 volts. There is provided a digital counting means 130 having an input connected to a line 132 from a source of character code generator clock or timing pulses which will be described in detail presently. Another input of counter 132 which is the reset input is connected to line 134 and when a signal is present thereon counter 130 is reset to zero total count as is readily apparent to those skilled in the art. In the system of the present invention, counter 130 is reset upon completion of the generation of each symbol or character commanded by the output of computer 30. Counter 130 which provides a digital signal representation of the total or accumulated count of pulses from line 132 on the output terminals thereof. In the system of the present invention, counter 130 will count up to thirty five before being reset to zero and therefore has six output terminals on which digital signals representing the count appear. The reason for this particular mode of operation will be explained hereafter. The three high order bit output terminals are connected by lines 135, 136 and 137 to resistors 138, 139 and 140, respectively. Resistors 138-140 are connected together through a resistor 141 to ground. Resistors 138-140 comprise a resistive network which serves to convert the signal output from counter 130 into a step or staircase waveform. Every eighth count produces a new step, that is from the count of one to the count of seven the voltage on line 142 is at a constant level and at the count of eight the voltage rises instantaneously to a new value and remains there until the count of fourteen and then rises by the same amount to the next level at the count of fifteen, etc. This continues for a total count of thirty five thereby generating five steps. In this connection, resistor 138 has a magnitude of about 51.1K, resistor 139 a magnitude of about 100 K resistor 140 a magnitude of about 200 K. The resulting step waveform on line 142 is connected to the input of a buffer amplifier 143, the output of which is present on a line 144.

The operation of counting means 130 is utilized also to generate a step or staircase waveform which is present on line 106 connected to the system of FIG. 2. In particular, the three low order bit outputs of counter 130 are connected to lines 146, 147 and 148. Line 146 is connected to a resistor 149, line 147 is connected to a resistor 150 and line 148 is connected to a resistor 151. Resistors 149-151 are connected together and to a resistor 152 to ground. The resistors 149-151 comprise a network which converts the successive count outputs of counting means 130 into a step or staircase waveform which is available on line 106. Each count produces a new step up to seven steps in generating the waveform on line 106, whereupon at the eight count the voltage returns to the reference level and again increases stepwise for the next seven counts and the procedure repeats. Thus for each step in the waveform on line 144 in FIG. 3 there are seven steps in the waveform on line 106. Resistor 149 has a magnitude of about 200 K, resistor 150 has a magnitude of about 100 K, and resistor 151 has a magnitude of about 51.1 K. Lines 146-148 connected to the output of counting means 130 also are connected to a logic network including inverters 153, 154 and Nand gates 155, 156 for providing signals on lines 158, 159 for synchronizing operation of this portion of the apparatus with another portion in a manner which presently will be described. The clock or timing pulses appearing on line 132 also are connected through line 160 to inputs of Nand gates 155 and 156.

The horizontal staircase or step waveform on line 144 providing the character or symbol component of the horizontal deflection signal is switched periodically into and out of the circuit including line 44 while a conventional sawtooth waveform providing the analog signal component of the horizontal sweep or deflection signal is switched periodically out of and into the circuit in the following manner. Line 144 is connected to a first voltage controlled switching means 164, the control terminal of which is connected to line 128 in the circuit of FIG. 2. Thus when the switch 112 in FIG. 2 connects the character of symbol component of the vertical deflection signal into line 42 switch 164 simultaneously is closed to connect the character or symbol component of the horizontal deflection signal through a potentiometer 166, resistor 167 and amplifier 169, to line 44. Adjustment of potentiometer 166 controls the width of the character image impressed on display 10. A sawtooth waveform is present on a line 174 connected to a second voltage controlled switching means 176 in the circuit of FIG. 3. According to a preferred mode of the present invention the sawtooth waveform varies in amplitude between about + 0.05 volts and +2.8 volts. A timing pulse having a frequency twice that of the multiplexing signal is present on a line 178 in the circuit of FIG. 3 to provide a sweep trigger signal at the output of an amplifier 180. Each trigger pulse preferably has a duration of about five microseconds. This is applied to the circuit components shown in FIG. 3 to provide the sawtooth waveform on line 174. The control terminal of switching means 176 is connected by a line 184 to the collector terminal of a transistor 186, the emitter terminal of which is grounded and the base terminal of which is connected through a resistor 187 to the output of a Nor gate 188. One input to Nor gate 188 is line 127 from the circuit of FIG. 2. Thus when the multiplexing signal is at a level closing switch 99 in the circuit of FIG. 2, switch 176 is closed to transmit the sawtooth waveform on line 174 through an amplifier 190, resistor 192, and amplifier 169 to line 44. Another input of Nor gate 188 is connected by a line 194 to the reset signal present on line 134 in the circuit of FIG. 2. This is for the purpose of closing switch 176 to transmit the sawtooth waveform after generation of the character or symbol is completed as will be described in further detail presently.

FIGS. 4 and 5 illustrate in detail the portion of the apparatus of the present invention for producing the blanking signals present on line 46 of FIG. 1. The three bit binary code output from computer means 30 is present on lines 200, 201 and 202 which are connected to the input of code synchronizing means 32 which comprises a flip-flop or latch element 204. Lines 200-202 also are connected as inputs to a Nor gate 206, the output of which is connected through an inverter 208 to an arrangement of flip-flops 210 and 212 for synchronizing the presence of the code signals on lines 200-202 with the operation of analog to digital converter 20. A line 214 connects flip-flop 212 to line 324 in the circuit of FIG. 2 on which the A/D Control signal is present for operating converter 20. The output of flip-flop 210 on line 216 is connected by line 217 in controlling relation to latch or flip-flop 204, and line 216 also is connected by a line 218 to a circuit (not shown) for confirming that a symbol or character is to be generated. The three bit code then is inserted in character memory system 34. In particular, output of flip-flop 204 is connected by lines 220, 221 and 222 to a first set of inputs of a digital switching means 224 similar in operation to digital switches 56 and 72 shown in FIG. 2. Switch 224 is connected to the inputs of shift register means 226 which in the present instance comprises three dynamic shift register elements controlled by clock pulses on line 82 which is connected to the register elements in a manner similar to that of the elements of register means 76. The outputs of shift register means 82 are available on lines 228, 229 and 230 in the form of a three bit code which is delayed by sequencing through the register 82 and by recirculation of the outputs back to digital switching means 224 in a manner similar to that of memory system 24 of FIG. 2. Digital switch 224 is controlled by signals on lines 87 and 88. The three bit code present on lines 228-230, representative of the category in which the analog signal is placed by computer means 30, thus is delayed in memory system 34 so as to be in synchronism with the digital words delayed by memory 24.

Referring now to FIG. 3, lines 228-230 are applied to the input of a logic network for converting the three bit code in a six bit representation thereof. The logic network includes flip-flops 232, 234 and R36 and Nor gates 237-243. Each of the flip-flops 232-236 provides both a true and complement output both of which are applied to the network of Nor gates 237-243, whereby for each different code represented by bits on lines 228-230 a logical one will exist on only one output at a time of the Nor gates 237-243. When no character is present there will be no logical one at any of the outputs of gates 237-243. Since seven Nor gates are provided, one can be used for a spare function. A flip-flop 244 is included in the network and the complement output thereof is used for synchronizing other portions of the circuit of FIG. 5 as will be described presently. The true output of flip-flop 244 provides the reset signal on line 134 connected to the circuit of FIG. 3 as previously described. The outputs of Nor gates 237-243 are connected to a diode matrix designated generally 246 in FIG. 4. Diode matrix 246 is provided for generating the proper ASCII code to command or address a character code generator 248. The ASCII code is well known to those skilled in the art, and the relationship used in the present invention between the code quantities, three bit input code on lines 228-230 and symbols or alphanumeric characters is shown in the following table.

Table I ______________________________________ ASCII Code Input Code Symbol Or Gate 000000 000 -- -- 011010 001 Z 239 000010 010 B 240 001110 011 N 241 000001 100 A 242 010110 101 V 243 001000 110 H 237 001100 111 L 238 ______________________________________

The middle column includes binary representations of the code signal inputs of lines 228-230. In the present instance the signal on line 228 represents the most significant bit of each code which bit is the left-hand bit of each code in Table I. Accordingly, the right-hand bit of each code is the least significant bit and the signal representing it is on line 230. The symbols or alphanumeric characters corresponding to the input codes are shown in Table I, the selection or correspondence being a matter of design choice, and the particular Nor gate developing a logical one output for the corresponding signal is indicated by the numbers in the right hand column of Table I. The correspondence between Nor gates 237-243 and the symbols or characters again is a matter of design choice.

The character of symbol code generator 248 preferably comprises a read only memory, for example a Fairchild No. 3257, which provides output codes representing vertical columns or components of a particular symbol or alphanumeric character. In particular, according to a preferred mode of the present invention, each character or symbol is described in code form by a five by seven dot matrix pattern including five columns and seven rows. Thus, character code generator 248 will produce for each symbol or character five digital words, each seven bits in length, corresponding to each vertical column making up a character or symbol. For example in generating the letter H, all seven bits of the first output word would be ones. This word disposed vertically represents the left-hand vertical line of the letter H. The second to fourth output words would include all zeros except for the middle bit which would be a one. These words all disposed vertically represent the horizontal line of the letter H. Then the final or fifth word would contain all ones. This word disposed vertically represents the right-hand vertical line of the letter H. The output words from character code generator 248 are applied as inputs to a parallel to serial converter 250 such as an RCA CD 4021 converter. The serial output of converter 250 is applied through an inverter 252 to logic network including Nand gates 253, 254 and 255, and the output of the network is translated through a buffer amplifier 256 to line 46 on which the blanking pulses are provided. Thus for each character or symbol to be generated a series of 35 digital signals will be transmitted serially from the output of converter 250 to describe a character. Each of these digital signals has one of two logical values, and one of those values will cause generation of a blanking pulse for preventing the electron beam from developing a visual spot at the particular location on the screen of display means 10, and the other value will prevent generation of a blanking pulse so that a visual spot is developed. This method of generating a visual image on the screen of a cathode ray tube is well understood by those skilled in the art. The blanking pulses are moved on the screen of display means 10 under control of the character or symbol components of the vertical and horizontal deflection signals in a manner which will be described presently. A line 260 connects one input of Nand gate 253 to a network for controlling the width of each spot by adjustment of a potentiometer 262 connected in a circuit including an amplifier 264 and for controlling spot delay as determined by the setting of a potentiometer 266 included in the circuit. Line 132 on which the character code generator timing or clock pulses are present is connected through an amplifier 268 to the spot adjustment network and through an inverter 270 to the parallel to serial converter 250 for timing the operation thereof. The operation of converter 250 is controlled or synchronized with the generation of the vertical staircase or step waveform by the circuit of FIG. 3 through connection by line 158. Similarly, the operation of character code generator 248 is controlled or synchronized with generation of that waveform in being connected to line 159 from the circuit of FIG. 3. A line 272 connects the complement output of flip-flop 244 to a control input of character code generator 248 for signalling that a character or symbol is to be generated. A line 274 connects generator 248 with a reset input of flip-flop 236 with and a set input of flip-flop 244 to inform the logic network when generation of a character has been completed. The multiplexing signal present on line 100 is inverted by inverter 276 and used for clocking flip-flop 244. The inverted multiplexing signal also is connected by a line 278 to a reset input of character code generator 248 and to Nand gate 254. A second input of Nand gate 255 is connected to line 179 from the circuit of FIG. 3 for applying to gate 255 the sweep trigger signals which control generation of the sawtooth waveform in the circuit of FIG. 3. These connections to gates 254, 255 insure that blanking pulses are not transmitted during the information or analog signal component of the vertical and horizontal deflection signals.

FIGS. 6 and 7 illustrate in further detail the clock and control circuits designated 40 in the system of FIG. 1. A system clock 300 in the circuit of FIG. 6 generates clock or timing pulses having a frequency of 410 kilohertz and are available on output lines 301 and 302. Clock 300 can be of various forms readily familiar to those skilled in the art, for example a unijunction oscillator circuit. Clock pulses on line 301 are processed by a logic network including gates 304-306 and an amplifier 307 to provide the character generator clock pulses having a frequency of 133.6 kiloherz available on line 132 for connection to appropriate components of the system as previously described. Clock pulses on line 302 are applied to the input of a flip-flop 308, the complement output of which is connected to a monostable circuit 310. A variable resistor 311 included in circuit 310 adjusts the width of the clock pulses produced thereby. The true output of flip-flop 308 together with the output of monostable circuit 310 are applied to inputs of a digital phase splitting circuit 312. Circuit 312 operates as a switch to alternately provide clock pulses on an output line 314 and control signals on lines 316, 318. Clock pulses on line 314 are applied to the input of a first digital counter 320, one output of which is connected to the input of a second digital counter 322. The outputs of counter 320 and some outputs of counter 322 together with signals on lines 316, 318 are connected to portions of a logic network as shown in FIG. 6 to produce the Read timing signals on line 66 for controlling the operation of digital switches 56 and 72 in the circuit of FIG. 2 and the digital switch 224 shown in FIG. 4 through the connections of lines 87, 88. The network also produces memory clock or timing pulses appearing on line 70 and 82 for controlling the shift registers 60 and 76 in the circuit of FIG. 2 and also the shift register 226 included in the circuit of FIG. 4. The network shown in FIG. 2 also generates the Store Control signals on line 53 for controlling flip-flop 52 in the circuit of FIG. 2. Appropriate outputs of both counters 320 and 322 are applied to the input of another logic network for generating A/D Control signals on line 324 which are connected to analog to digital converter 20 for controlling the operation thereof. One output of counter 322 is connected to line 178 and provides the sweep trigger signals used in the circuit of FIG. 3 for generating the sawtooth waveform. Another output of counter 322 provides multiplexing signal and is connected to line 100. Finally, another output of counter 322 is connected by a line 326 to the control portion of the circuit 40. A line 328 from that control portion is connected to the input of one of the Nand gates in the logic network which generates the clock pulses on line 82.

FIG. 7 shows in further detail the control portion of the circuit designated 40 in FIG. 1. A control switch 340 for example a manually-operated switch located on the control panel of the apparatus, connects a bias voltage to one of three control terminals 342, 344 and 346 for placing the system in either the lock, run or hold modes, respectively. These various modes will be defined in detail presently. External control lines are connected to control lines 348, 350 and 352 of the circuit of FIG. 7. The logic network develops a Delay Dump control signal on line 60 and also a Video Dump signal on line 86, both lines being connected in the circuit of FIG. 2, for a purpose to be described. Another portion of the logic network develops a Hold or Run control signal on a line on line 328 which is connected in a portion of the logic network of FIG. 6. In particular, a logical one signal level on line 328 commands the Run mode and a logical zero on line 328 commands the Hotel mode. Line 326 from an output of counter 322 in the circuit of FIG. 6 is connected to an input of a flip-flop in the circuit of FIG. 7.

FIG. 8 is a graph illustrating clock or timing signal waveforms generated by the circuit of FIG. 6. The relative spacing in time is not to scale, and each of the pulse voltage waveforms typically varies between zero volts and plus five volts in amplitude. Waveform 360 at the top of FIG. 6 illustrates the multiplexing signal present on line 100 in various portions of the circuit. Multiplexing signal 360 according to a preferred mode of the present invention is a fifty pulse per second square wave wherein each pulse has a duration of about 10,000 microseconds or 10 milliseconds. Waveform 362 is the timing signal present on line 66, also called the Read signal, which controls the operation of digital switch 56 and digital switch 72 in the circuit of FIG. 2. Each of the pulses in waveform 362 has a duration of about 5 microseconds, and the time between adjacent pulses also is 5 microseconds. The relative time spacing between the trailing edge of the second pulse in waveform 362 at the left of FIG. 8 and the leading edge of multiplexing signal 360 is about 1 microsecond. Similarly, the relative time spacing between the trailing edge of the second pulse in waveform 362 at the right in FIG. 8 and the trailing edge of multiplexing signal 360 is about one microsecond. Waveform 364 in FIG. 8 is the timing signal available on line 324 of FIG. 6 which is used to control the operation of analog to digital converter 20 in the system of FIG. 1. According to a preferred mode of the present invention, the time between pulses is about 5,000 microseconds or 5 milliseconds. The next waveform 366 in FIG. 8 represents the clock or timing pulses present on lines 82 in FIG. 6 for controlling shift register means 76 in the circuit of FIG. 2 as well as shift register means 226 in the arrangement of FIG. 4. The dotted line pulses included in waveform 366 are present only when the system is in the Run mode. The next waveform 368 is the Store Control signal present on line 53 which controls the operation of flip-flop 52 in the circuit of FIG. 2. Waveform 370 is a run-gate signal which functions to advance the memory to accept new data and the duration of the pulse is about 19.2 microseconds. The waveform 372 represents the timing pulses present on line 70 for controlling the operation of shift register means 60 in the arrangement of FIG. 2.

The first pulse at the left of the A/D Control waveform 364 as illustrated in FIG. 8 triggers analog to digital converter 20 to make a first sampling of the analog voltage output of amplifier 18 and generate a first digital word representative of the amplitude thereof. The first pulse at the left of Store Control waveform 368 triggers flip-flop 52 to accept this first word from converter 20. The next pulse in waveform 364, occuring in time shortly after the pulse of waveform 368, commands converter 20 to make a second sampling of the analog voltage and generate a second word in response thereto. In response to the pulse of waveform 370, the memory system is advanced to accept new words. The two pulses at the right of the Read waveform 362 as viewed in FIG. 2 cause the two words to be read into the shift register memory 60 in conjunction with the last pulse in the waveform 368. In particular, the first word will be present in flip-flop 53 and the first pulse of waveform 362 causes this to be transmitted to the register 60. The pulse of Store Control 368 occurs as soon as the first pulse in Read waveform 362 disappears causing the word from converter 20 to be inserted directly into the register 60 in response to the occurrence of the second pulse in waveform 362. It will be noted that the foregoing sequence of events occurs during a time interval when multiplexing signal 360 represented by waveform 360 is at one of its two levels. This time is 10,000 microseconds according to a preferred mode of the present invention. The foregoing sequence of events is repeated when multiplexing signal switches to the other amplitude level as indicated by the fact A/D Control waveform 364 includes a pulse having a leading edge which coincides in time with the trailing edge of the multiplexing signal 360. Shift registers 76 and 226 are shifted or sequenced by the pulses of waveforms 366, and shift register 60 is shifted by the pulses of a waveform 372.

The system of the present invention operates in the following manner. A signal containing data or information to be examined by display means 10 is present on line 16. The input signal can be of the analog type having parameters which vary in accordance with data or information, such as a physiological signal, for example a signal from electrocardiographic monitoring, which is a nonrecurrent, relatively low frequency signal. The system of the present invention is contemplated for use, however, in studying other types of signals having an information content.

The input signal is amplified and then sampled by analog to digital converter 20 at a rate determined by the frequency of A/D Control waveform 364, preferably about three to four times the maximum frequency of the input signal. Converter 20 generates digital words, preferably eight bits in length signifying the instantaneous amplitude of the analog signal at the time of sampling. The digital words are transferred to memory system 22, in particular to shift register means 60, under control of flip-flop 52 and digital switching means 56 at a rate determined by the frequency of Store Control waveform 368 and Read waveform 362. Once inserted, the digital words progress sequentially through the shift register means 60, and at the output of register means 60 the words are sent back to digital switch 56 to be recirculated a prescribed number of times before being discarded. According to a preferred mode of the present invention, each word remains in memory system 22 for about 2.56 seconds.

The information or data signal present on line 16 also is applied by line 29 to the input of computer means 30. The signal is sampled by an analog digital converter, and the resulting digital words are processed by the computer means 30 under control of a program for placing the signal in one of a plurality of categories depending upon particular characteristics thereof. Upon determining the category, computer means 30 generates a three bit code representative thereof. One form of computer found to perform well in the system of the present invention is model PDP-11 of the Digital Equipment Corp. A program for controlling such a computer to convert electrocardiographic signals into digital codes corresponding to several categories is described in an article entitled "Detection of Premature Ventricular Contractions With A Clinical System For Monitoring Electrocardiographic Rhythms" by G. C. Oliver et al appearing at pages 523-541 of Computers and Biomedical Research, Vol. 4, October 1971. The three bit code at the output of computer 30 is transmitted to the code synchronizing circuit 32 for synchronizing the code signal in time with the rest of the system. This would not be necessary if the system were clocked directly from computer means 30.

At this stage in the operation of the system, signals representative of the three bit code from computer 30 are present on lines 220-222 in the circuit of FIG. 4 and an eight bit word representative of a sampled portion of the data signal is available at the output of memory means 22. The 2.56 second delay provided by memory means 22 is to give computer means 30 ample time to examine the information signal and generate the appropriate code. The eight bit words from memory means 22 and the three bit code word from computer 30 are transmitted through the video memory system 24 and character code memory system 34, respectively, and recirculated therein for a prescribed time determined by the requirements of the refreshed or non-fading display. According to a preferred mode of the present invention, the memory system 24 and 34 provide a delay of about 5.12 seconds whereby the visual image of the information signal and the associated symbol or character remain on the screen of display means 10 for about 5.12 seconds, a period of time longer than the actual duration of the portion of the information signal being analyzed.

The eight bit words from the output of memory system 24 are converted to corresponding analog signals by converter means 26, are filtered and amplified, and are available on line 97 for connection to line 42 under control of switch 98. The signal on line 97 thus comprises the component of the vertical deflection signal for display means 10 for displaying the information or analog signals thereon. The component of the vertical deflection signal for displaying the character or symbol commanded by the three bit code is present on line 106 in the circuit of FIG. 2 and is generated by counter 130 in the circuit of FIG. 3 in response to the character code generator timing signals present on line 132 from the circuit of FIG. 6. This is a step or staircase type waveform which forms part of a local raster for forming a dot matrix display of the symbol or character and is connected to line 42 in the circuit of FIG. 2 under control of switch 112. Thus the vertical deflection signal on line 42 is switched between the data or analog signal and the character or symbol trace at a rate determined by the frequency of the multiplexing signal present on line 100 in the circuit of FIG. 2. The spacing between images on display 10 is controlled by potentiometer 121. According to a preferred mode of the present invention, the frequency of the multiplexing signal is 50 pulses per second. Therefore, the vertical deflection signal on line 42 provides 100 sweeps per second to give 50 displays per second. That is, 50 traces of the analog signal and 50 traces of the character signal occur during each second of time. The composite vertical deflection signal is illustrated by waveform 380 in the graph of FIG. 9.

The composite horizontal deflection signal present on line 44 is generated in the following manner. The component of the signal for tracing the horizontal portion of the analog or data signal comprises a standard sawtooth waveform having a frequency determined by the timing pulses present on line 178 from the circuit of FIG. 6 and is available on line 174 in the circuit of FIG. 3 for connection to line 44 under control of switch 176. Switch 176 is closed during the portion of the sweep when the analog or data signal is being traced. The component of the horizontal deflection signal for tracing the character or symbol comprises a staircase or step waveform generated by counter 130 in the circuit of FIG. 3 under control of the character code generator timing pulses on line 132. This waveform is present on line 144 and is connected to line 44 under the control of switch 164. Referring now to the circuits of FIGS. 2 and 3 together, it will be seen that when switch 98 connects the analog or data signal component to line 42 switch 176 connects the sawtooth waveform comprising the analog or data signal component ot line 44. In particular, when the multiplexing signal present on line 100 in FIG. 2 has a relatively high value this causes the network comprising transistors 102 and 104 to apply a relatively high voltage to switch 98 thereby closing the same. This same high value of multiplexing signal 100 is connected by line 127 to Nor gate 188 which causes transistor 186 to place a relatively high voltage on line 184 thereby closing switch 176. When the multiplexing signal on line 100 switches to its relatively low value opening switch 98 and closing switch 112 in FIG. 2, switch 176 in FIG. 3 is opened because the signal on line 127 disappears and simultaneously switch 164 is closed due to the fact that line 128 connects a relatively high voltage from the circuit of FIG. 2 to switch 164. Thus, the stepwise or staircase waveform is connected to line 44. When this waveform disappears, as controlled by the presence of a reset signal on line 134 connected to counter 130, the reset signal also is connected by line 194 through Nor gate 188 again causing transistor 186 to connect a relatively high voltage to switch 176 thereby returning the sawtooth waveform on line 174 to line 44. The composite horizontal signal on line 144 is represented by waveform 382 in FIG. 9. It will be noted that the lefthand portion of waveform 32 is of the sawtooth type and corresponds in time to the analog or data portion of the waveform 380. Likewise, the righthand portion of waveform 382 comprises the stepwise or staircase waveforms corresponding in time to the similar waveforms in the righthand portion of waveform 380.

The signals on line 46 applied to display 10 are used to form the dots in a dot matrix pattern forming an image of the symbol and are generated in the following manner. Signals representative of the three bit code provided by computer means 30 are present on lines 228-230 in the circuit of FIG. 5. The three bit code is converted by flip flops 232, 234 and 236 to a six code and this, in turn, is converted to a logical representation of the particular symbol or character by the network of gates 237-243. In particular, depending upon which of seven symbols or characters is selected, a logical one will appear at only one of the outputs of gates 237-243. The remaining gates have a logical zero output. This in turn is applied to diode matrix 246 which generates the proper address for the character code generator or read only memory 248. The memory 248 provides a parallel output of code words representing the vertical columns of a dot matrix representation of the symbol or character to be generated, and the number of code words equals the number of columns in the dot matrix representation of the symbol or character. Thus memory 248 has stored therein a plurality of groups of code words, the number of groups being equal to the number of characters or symbols used in the system, and each group being addressable by diode matrix 246. The output of memory 248 is clocked in synchronism with the staircase waveform provided by counter means 130 in the circuit of FIG. 3 through the connection by line 159. The code words from memory 248 are converted to serial bits or signals by the converter 250 and appear as pulses on line 46.

The blanking pulse positions, i.e., a pulse signal for forming dots, are moved vertically under control of the staircase or step component of the vertical deflection signal on line 44 which includes seven steps, one for each dot position in the vertical column of the matrix. When a vertical column is completed, that is after seven steps, the step or staircase component of the horizontal deflection signal on line 44 moves the trace to the next column whereupon the blanking pulse positions or dot forming signal are again moved vertically for seven steps under control of the step component of the vertical deflection signal. This continues for five rows of the character or symbol being generated. Thus the step waveform of the horizontal deflection signal contains five steps, and for each of these steps there are seven steps in the step waveform of the vertical deflection signal. Where a dot is to appear on the screen of display 10 there will be no blanking pulse and where no dot is to appear there will be a blanking pulse as is readily understood by those skilled in the art. According to a preferred mode of the present invention the dot matrix representation or pattern employs a total of 35 blanking pulse positions for the generation of each symbol or character.

The system of the present invention therefore provides a visual image on the screen of display means 10 of the information or analog signal and a visual image of a selected symbol or alphanumeric character categorizing the signal. The images appear in spaced but corresponding relationship to each other. As shown in FIG. 1, display means 10 has a visual image thereon of an analog signal comprising two successive heartbeat waveforms. Computer means 30 has determined that these beats are normal, and therefore the system has formed a visual image of the character N below each wave indicating that it is considered to be normal. The system including display 10 is of the refreshed or non-fading type so that the information signal and the symbol or character remain on the display screen for an extended period of time to permit prolonged visual analysis. In the normal mode of operation of the system, also known as the Run mode, switch 340 in the circuit of FIG. 7 engages contact 344 to produce a logical one output on line 328 thereby maintaining the images on display means 10 for a predetermined time, preferably about 5.12 seconds, whereupon the next waveform and its corresponding symbol or character will appear. If data of special interest is on display, the system can be put into the Hold mode by moving switch 340 to contact 346 thereby putting a logical zero output on line 328. This will stop the progress of the data signal and the symbols or characters and hold the desired information on the screen of display means 10 indefinitely. No new data is entered into the memories and the data already in the memory is constantly recirculated. The waveform as displayed is exactly synchronized with the horizontal sweep signal. The Delay Dump and Video Dump control function providing signals on lines 69 and 86 enable the computer means 30 to override the system. This could arise when the computer senses an alarm situation thereby enabling the system to monitor the patient in alarm or to switch to that particular patient. The system also can be operated in what is known as a lock mode by moving switch 340 to contact 342 to give exclusively local control on the system thereby preventing computer 30 from assuming control of the system.

It is therefore apparent that the present invention accomplishes its intended objects. While a single embodiment of the present invention has been described in detail, this is for the purpose of illustration, not limitation.

Claims

1. In combination:

a. display means of the type having a display trace sweep for providing a visual image in response to signals applied thereto;

b. input means adapted to be coupled to a signal representing information;

c. means connected to said input means for examining said information signal and for providing a signal representation of a symbol selected according to the nature of said information signal; and

d. signal applying means connected to said input means and to said means providing said signal representation of a symbol for applying said information signal and said signal representation to said display means for providing visual images of said information signal and said symbol simultaneously on said display means in corresponding relation to each

2. The combination according to claim 1, wherein said signal applying means includes refresh display memory means whereby the images of said information signal and said symbol are maintained on said display means

3. The combination according to claim 1, wherein said display means is of the cathode ray tube type and said signal applying means comprises:

a. means for applying to said display means a composite vertical deflection signal which alternately traces the vertical components of said information signal and said symbol;

b. means for applying to said display means a composite horizontal deflection signal which alternately traces the horizontal components of said information signal and said symbol; and

c. means for applying to said display means blanking signals to form a

4. The combination according to claim 3, wherein said means for applying said composite vertical deflection signal comprises:

a. means for generating a step signal wherein each step corresponds to a vertical component of said symbol; and

b. controlled switching means for alternately connecting the vertical component of said information signal and said step signal to said display

5. The combination according to claim 4, wherein said means for generating a step signal comprises:

a. timing pulse generating means;

b. counting means having an input connected to said timing pulse generating means for counting said timing pulses and providing output signals representing each count; and

c. means connected to the output of said counting means for converting

6. The combination according to claim 3, wherein said means for applying said composite vertical deflection signal comprises:

a. means including memory means for converting said information signal into a refreshed signal;

b. means for generating a step signal wherein each step corresponds to a vertical component of said symbol; and

c. controlled switching means for alternately connecting the outputs of said converting means and said step signal generating means to said

7. The combination according to claim 6, wherein converting means comprises:

a. means for sampling said information signal and providing digital word signals signifying the instantaneous value of a parameter of the signal at the time of sampling;

b. memory means connected to the output of said sampling means for delaying said words for a predetermined time; and

c. converter means connected to the output of said memory means for converting digital words released from said memory means into a signal

8. The combination according to claim 4, further comprising:

a. switching signal producing means connected to said switching means for alternately connecting said vertical signal components at the frequency of said switching signal; and

b. signal spacing means connected to said switching signal producing means and to the output of said switching means for spacing apart on said display means the vertical components of said information signal and said

9. The combination according to claim 3, wherein said means for applying said composite horizontal deflection signal comprises:

a. means for generating a horizontal sweep signal;

b. means for generating a step signal wherein each step corresponds to a horizontal component of said symbol; and

c. controlled switching means for alternately connecting said horizontal

10. The combination according to claim 9, wherein said means for generating a step signal comprises:

a. timing pulse generating means;

b. counting means having an input connected to said timing pulse generating means for counting said timing pulses and providing output signals representing each count; and

c. means connected to the output of said counting means for converting the count representation into said step signal in a manner such that each step

11. The combination according to claim 3, wherein said means for applying blanking signals comprises:

a. means for providing a code as determined by the symbol which is selected;

b. means for converting said code to a plurality of digital words representing vertical and horizontal components of the symbol; and

c. means for converting said digital words to signals for application to

12. The combination according to claim 11, wherein said code providing means comprises computer means for examining said information signal, placing said signal in one of a plurality of categories as determined by characteristics of said signal, and generating said code as determined by

13. The combination according to claim 11, wherein said symbol is represented by a dot matrix pattern and wherein converting means produces digital words each including a number of bits equal to the number of dot positions in a vertical column of the matrix, the number of digital words being equal to the number of dot positions in a horizontal row of the

14. A system for displaying signals containing information comprising:

a. display means of the type having a display trace sweep for providing a visual image in response to signals applied thereto;

b. first signal generating means connected to said display means for providing a visual image of a signal representing information on said display means said first signal generating means producing horizontal and vertical deflection signals;

c. second signal generating means connected to said display means for providing a dot matrix pattern forming a visual image of a selected symbol and comprising means producing signals for forming the dots of said matrix pattern as determined by the particular symbol selected and means producing horizontal and vertical deflection signals for moving said dot forming signals stepwise in the rows and columns of the matrix to from a visual image of the symbol; and

d. means for synchronizing the generation of said information signal image with said dot matrix image of said symbol whereby both images are viewed together on said display means, said synchronizing means including controlled switching means for alternately connecting the vertical and horizontal deflection signals produced by said first and second signal generating means to said display means in a manner such that each sweep alternates between the information signal and the dot matrix pattern

15. A system as defined in claim 14, wherein said first and second signal generating means each includes memory means whereby said display means is of the refreshed type enabling prolonged viewing of the images formed

16. A system as defined in claim 14, wherein said means producing dot forming signals comprises:

a. means providing a code as determined by the symbol which is selected;

b. means for converting said code to a plurality of digital words representing vertical and horizontal components of said matrix; and

17. A system as defined in claim 16, wherein said converting means produces digital words each including a number of bits equal to the number of dot positions in a vertical column of the matrix, the number of digital words being equal to the number of dot positions in a horizontal row of the

18. A system as defined in claim 14, wherein said means producing deflection signals comprises:

a. a source of timing pulses;

b. digital counting means having an input connected to said source of timing pulses for counting said timing pulses and providing digital output signals representing each count;

c. means connected to the low order bit positions of the counter output for converting the count representations into a step signal comprising the vertical deflection signal; and

d. means connected to the high order bit positions of the counter output for converting the count representation into a step signal comprising the horizontal deflection signal; and

e. whereby a plurality of steps in the vertical deflection signal are

19. A system for displaying signals containing information comprising:

a. display means of the type having a display trace sweep for providing a visual image in response to signals applied thereto;

b. means for providing a signal representing information;

c. means for providing a signal representation of a symbol selected according to the nature of said information signal;

d. means operatively connected to said information signal providing means for applying to said display means a composite vertical deflection signal which alternately traces the vertical components of said information signal and said symbol;

e. means for applying to said display means a composite horizontal deflection signal which alternately traces the horizontal components of said information signal and said symbol; and

f. means operatively connected to said symbol representation signal providing means for applying to said display means blanking signals to form a visual image of said symbol and comprising means for providing a code as determined by the symbol which is selected, means for converting said code to a plurality of digital words representing vertical and horizontal components of the symbol, and means for converting said digital words to signals for application to said display means to form a visual

20. A system as defined in claim 19, wherein said code providing means comprises computer means for examing said information signal, placing said signal in one of a plurality of categories as determined by characteristics of said signal, and generating said code as determined by

21. A system as defined in claim 19, wherein said symbol is represented by a dot matrix pattern and wherein converting means produces digital words each including a number of bits equal to the number of dot positions in a vertical column of the matrix, the number of digital words being equal to

22. A system for displaying signals containing information comprising:

a. display means of the type having a display trace sweep for providing a visual image in response to signals applied thereto;

b. means for providing a signal representing information;

c. means for providing a signal representation of a symbol selected according to the nature of said information signal;

d. means operatively connected to said information signal providing means for applying to said display means a composite vertical deflection signal which alternately traces the vertical components of said information signal and said symbol, said composite vertical signal applying means comprising means for generating a step signal wherein each step corresponds to a vertical component of said symbol and controlled switching means for alternately connecting the vertical component of said information signal and said step signal to said display means;

e. means for applying to said display means a composite horizontal deflection signal which alternately traces the horizontal components of said information signal and said symbol, said composite horizontal signal applying means comprising means for generating a horizontal sweep signal, means for generating a step signal wherein each step corresponds to a horizontal component of said symbol, and controlled switching means for alternately connecting said horizontal sweep signal and said step signal to said display means; and

f. means operatively connected to said symbol representation signal providing means for applying to said display means blanking signals to

23. A system as defined in claim 22, wherein said step signal generating means of said composite vertical signal applying means comprises:

a. timing pulse generating means;

b. counting means having an input connected to said timing pulse generating means for counting said timing pulses and providing output signals representing each count; and

c. means connected to the output of said counting means for converting

24. A system as defined in claim 22, wherein said means for applying said composite vertical deflection signal further comprises memory means for

25. A system as defined in claim 22, wherein said means for applying said composite vertical deflection signal further comprises:

a. means for sampling said information signal and providing digital word signals signifying the instantaneous value of a parameter of the signal at the time of sampling;

b. memory means connected to the output of said sampling means for delaying said words for a predetermined time; and

c. converter means connected to the output of said memory means for converting digital words released from said memory means into a signal

26. A system as defined in claim 22, wherein said means for applying said composite vertical deflection signal further comprises:

a. switching signal producing means connected to said switching means for alternately connecting said vertical signal components at the frequency of said switching signal; and

b. signal spacing means connected to said switching signal producing means and to the output of said switching means for spacing apart on said display means the vertical components of said information signal and said

27. A system as defined in claim 22, wherein said step signal generating means of said composite horizontal deflection signal applying means comprises:

a. timing pulse generating means;

b. counting means having an input connected to said timing pulse generating means for counting said timing pulses and providing output signals representing each count; and

c. means connected to the output of said counting means for converting the count representation into said step signal in a manner such that each step

28. A system for displaying signals containing information comprising:

a. display means of the type having a display trace sweep for providing a visual image in response to signals applied thereto;

b. first signal generating means connected to said display means for providing a visual image of a signal representing information on said display means;

c. second signal generating means connected to said display means for providing a dot matrix pattern forming a visual image of a selected symbol and comprising means producing signals for forming the dots of said matrix pattern as determined by the particular symbol selected and means producing horizontal and vertical deflection signals for moving said dot forming signals stepwise in the rows and columns of the matrix to from a visual image of the symbol;

d. said means producing dot forming signals comprising means providing a code as determined by the symbol which is selected, means for converting said code to a plurality of digital words representing vertical and horizontal components of said matrix, and means for converting said digital words to sequential signals;

e. said code providing means comprising computer means for examining said information signal, placing said signal in one of a plurality of categories as determined by characteristics of said signal, and generating said code as determined by the particular category in which said signal is placed; and

f. means for synchronizing the generation of said information signal image with said dot matrix image of said symbol whereby both images are viewed

29. A system as defined in claim 28, wherein said first and second signal generating means each includes memory means whereby said display means is of the refreshed type enabling prolonged viewing of the images formed

30. A system as defined in claim 28, wherein each of said first and second signal generating means produces vertical and horizontal deflection signals and wherein said synchronizing means includes controlled switching means for alternately connecting the vertical and horizontal deflection signals to said display means in a manner such that each sweep alternates between the information signal and the dot matrix pattern forming the

31. A system for displaying signals containing information comprising:

a. display means of the type having a display trace sweep for providing a visual image in response to signals applied thereto;

b. first signal generating means connected to said display means for providing a visual image of a signal representing information on said display means;

c. second signal generating means connected to said display means for providing a dot matrix pattern forming a visual image of a selected symbol and comprising means producing signals for forming the dots of said matrix pattern as determined by the particular symbol selected and means producing horizontal and vertical deflection signals for moving said dot forming signals stepwise in the rows and columns of the matrix to form a visual image of the symbol;

d. said means producing deflection signals comprising a source of timing pulses, digital counting means having an input connected to said source of timing pulses for counting said timing pulses and providing digital output signals representing each count, means connected to the low order bit positions of the counter output for converting the count representations into a step signal comprising the vertical deflection signal, and means connected to the high order bit positions of the counter output for converting the count representations into a step signal comprising the horizontal deflection signal whereby a plurality of steps in the vertical deflection signal are provided for each step in the horizontal deflection signal; and

e. means for synchronizing the generation of said information signal image with said dot matrix image of said symbol whereby both images are viewed together on said display means.