Paper currency validator

Abstract

Longitudinally spaced and laterally spaced sensors are used to sense longitudinally spaced and laterally spaced areas on each inserted bill. The lateral spacing of those sensors enables one of those sensors to engage and sense part of the upper half, and enables the other of those sensors to engage and sense part of the lower half, of each inserted bill -- thereby making it possible to prevent the acceptance of a sheet of paper bearing just the upper half of an authentic bill and also making it possible to prevent the acceptance of a sheet of paper bearing just the lower upper half of an authentic bill. The longitudinal spacing of those sensors enables one of those sensors to engage and sense part of the leading half, and enables the other of those sensors to engage and sense part of the trailing half, of each inserted bill -- thereby making it possible to prevent the acceptance of a sheet of paper bearing just the leading half of an authentic bill and also making it possible to prevent the acceptance of a sheet of paper bearing just the trailing half of an authentic bill. In addition, the longitudinal spacing of those sensors enables those sensors to provide four signals which correspond to the longitudinally spaced and laterally spaced areas on an authentic bill and which are spaced apart in time; and thus makes it possible to use two sensors to provide four time-spaced signals. The two sensors of the paper currency validator are connected in series; and the series connecting of those sensors and the time-spacing of the signals corresponding to the longitudinally spaced and laterally spaced areas on an authentic bill make it possible for one amplifier to receive and amplify the signals from both of those sensors. The paper currency validator uses phase locked loops as frequency detectors, and thereby provides very compact, relatively inexpensive, and readily adjusted frequency detectors. One of these locked loops responds to signals which are developed as an authentic U.S. 1 dollar bill is engaged and sensed by the sensors, and the other of those phase locked loops responds to signals which are developed as an authentic U.S. 5 dollar bill is engaged and sensed by the sensors; and hence the paper currency validator can test the validity of authentic U.S. 1 dollar and 5 dollar bills. Additionally, the paper currency validator can respond to signals from a dispensing machine with which it is associated to selectively reject such 1 dollar bills, such 5 dollar bills, or all such 1 dollar and 5 dollar bills. The sensors of the paper currency validator engage and sense the border on each inserted authentic bill before they engage and sense the longitudinally spaced and laterally spaced areas on the bill -- thereby making it possible to reject any bill which does not have a border. The paper currency validator requires a number of specifically different events to occur within a corresponding number of specifically different time periods; and it utilizes timing circuits which include gates and a binary counter to determine the lengths of those time periods. In using timing circuits which include a binary counter and gates instead of using RC networks, the paper currency validator attains more precise control over the lengths of the time periods, and it does so at less cost and in a smaller space.

Description

FIELD OF THE INVENTION

The present invention relates to paper currency validators which are able to distinguish between authentic bills and spurious bills.

DESCRIPTION OF THE PRIOR ART

Fishel et al application Ser. No. 297,327 for Paper Currency Validator, which was filed on Oct. 13, 1972 now U.S. Pat. No. 3,845,469, discloses a paper currency validator which distinguishes between authentic bills and spurious bills. That paper currency validator performs a number of tests on each inserted bill; and the paper currency validator of the present invention performs improved versions of some of those tests and also performs some additional tests.

SUMMARY OF THE INVENTION

The present invention provides a paper currency validator which receives inserted bills and moves them past two sensors that are spaced apart both longitudinally and laterally of the path of those inserted bills. The lateral spacing of those sensors enables one of those sensors to engage and sense part of the upper half, and enables the other of those sensors to engage and sense part of the lower half, of each inserted bill. Consequently, that lateral spacing makes it possible for the paper currency validator to prevent the acceptance of a sheet of paper bearing just the upper half of an authentic bill, and also makes it possible to prevent the acceptance of a sheet of paper bearing just the lower half of an authentic bill. The longitudinal spacing of the sensors enables one of those sensors to engage and sense part of the leading half, and enables the other of those sensors to engage and sense part of the trailing half, of each inserted bill. Consequently, that longitudinal spacing makes it possible for the paper currency validator to prevent the acceptance of a sheet of paper bearing just the leading half of an authentic bill, and also makes it possible to prevent the acceptance of a sheet of paper bearing just the trailing half of an authentic bill. Furthermore, that longitudinal spacing enables the sensors to provide four signals which are spaced apart in time and which correspond to four longitudinally spaced and laterally spaced areas on an authentic bill. In this way, the paper currency validator is able to use two sensors to provide four time-spaced signals from four longitudinally spaced and laterally spaced areas on an authentic bill. It is, therefore, an object of the present invention to provide a paper currency validator which utilizes two longitudinally spaced and laterally spaced sensors to provide four time-spaced signals that correspond to four longitudinally spaced and laterally spaced areas on an inserted bill.

The two sensors of the paper currency validator provided by the present invention are connected in series. The series connecting of those sensors, and the time-spacing of the signals which correspond to the four longitudinally spaced and laterally spaced areas on an authentic bill, make it possible for one amplifier to receive and amplify the signals from both of those sensors. The use of a single amplifier is desirable because it avoids the cost of two amplifiers, and also because it avoids problems which could arise from the different responses which two individually different amplifiers could make to signals from the two sensors. It is, therefore, an object of the present invention to connect two sensors of a paper currency validator in series relation and to cause those sensors to apply time-spaced signals to the same amplifier.

The paper currency validator of the present invention uses phase locked loops as frequency detectors -- despite the fact that the oscillators of phased locked loops can, and do, change the frequencies of the signals generated thereby during normal operation of those phase locked loops, and despite the fact that the signals generated by the oscillators of phase locked loops can randomly be in phase with or displaced in phase from the signals applied to those phase locked loops. Specifically, phase locked loops have oscillators which establish center frequencies for those phase locked loops; and whenever the frequency of a signal, that is applied to the input of a phase locked loop, differs slightly from the center frequency of that phase locked loop, the oscillator of that phase locked loop will change the frequency thereof to "track" the frequency of that applied signal. This means that instead of having a fixed frequency, as do the frequency-sensing circuits of the said Fishel et al application, a phased locked loop has a frequency which can, and does, change during the normal operation of that phase locked loop. Also, the signal generated by the oscillator of a phase locked loop can be in phase with or displaced in phase from the signal applied to the input of that phase locked loop; and where the signal generated by the oscillator of a phase locked loop is displaced in phase from the signal applied to the input of that phase locked loop, that phase locked loop could sometimes require so much time to "track" and "lock up with" that input signal that it might fail to respond to that input signal. Also, where the signal generated by the oscillator of a phase locked loop is displaced in phase from the signal applied to the input of that phase locked loop, that phase locked loop can occasionally develop two output signals rather than just the desired output signal. As a result, the use of a phase locked loop as a frequency detector for a paper currency validator does not, without more, seem desirable. However, by equipping a phase locked loop with resistors and capacitors which narrowly limit the extent to which the frequency of the oscillator of that phase locked loop can change, and by providing circuitry which receives the signals from that phase locked loop and which will not respond to a series of fewer than three or more than five signals from that phase locked loop, the present invention makes it possible to use a phase locked loop as a frequency detector for a paper currency validator. It is, therefore, an object of the present invention to provide a paper currency validator with phase locked loops which have resistive and capacitive components that narrowly limit the extents to which the frequencies of the oscillators of those phase locked loops can shift, and also to apply the output signals of those phase locked loops to circuitry which can not respond to a series of fewer than three or more than five signals from either of those phase locked loops.

One of the phase locked loops responds to signals which are developed as an authentic U.S. 1 dollar bill is engaged and sensed by the sensors, and the other of those phase locked loops responds to signals which are developed as an authentic U.S. 5 dollar bill is engaged and sensed by those sensors. As a result, the paper currency validator provided by the present invention can determine the validity of U.S. authentic 1 dollar bills and U.S. authentic 5 dollar bills. That paper currency validator can respond to signals from a dispensing machine with which it is associated to selectively reject such 1 dollar bills, to reject such 5 dollar bills, or to reject all such 1 dollar and 5 dollar bills. As a result, if the dispensing machine is able to dispense change for a 1 dollar bill but not for a 5 dollar bill, the paper currency validator will respond to an appropriate signal from that dispensing machine to prevent the acceptance of further 5 dollar bills while continuing to accept 1 dollar bills. On the other hand, if the dispensing machine is able to dispense change for a 5 dollar bill but not for a 1 dollar bill, the paper currency validator will respond to an appropriate signal from that dispensing machine to prevent the acceptance of further 1 dollar bills while continuing to accept 5 dollar bills. If the dispensing machine is incapable of dispensing change for a 1 dollar bill as well as for a 5 dollar bill, the paper currency validator will respond to an appropriate signal from that dispensing machine to reject further 1 dollar bills as well as further 5 dollar bills. It is, therefore, an object of the present invention to provide a paper currency validator which can determine the validity of 1 dollar bills and 5 dollar bills and which can respond to signals from a dispensing machine with which it is associated to selectively reject further 1 dollar bills, to reject further 5 dollar bills, or to reject further 1 and 5 dollar bills.

The sensors of the paper currency validator provided by the present invention engage and sense the border on each inserted bill before they engage and sense the four longitudinally spaced and laterally spaced areas on that bill. The engaging and sensing of the border before the engaging and sensing of the laterally spaced and longitudinally spaced areas on the bill makes it possible for the paper currency validator to reject any bill which does not have a border. It is, therefore, an object of the present invention to provide a paper currency validator which checks the border on each inserted bill.

The paper currency validator requires a number of specifically different events to occur within a corresponding number of specifically different time periods; and it utilizes timing circuits which include gates and a binary counter to determine the lengths of those time periods. In using timing circuits which include a binary counter and gates instead of using R.C. networks, the paper currency validator attains more precise control over the lengths of those time periods; because R.C. networks necessarily include components which can tend to "drift." Even resistive and capacitive components which have low temperature coefficients experience some changes as the temperatures thereof change; and hence even R.C. networks which utilize components with low temperature coefficients can not provide the precise timing which is provided by the binary counter and the gates of the present invention. Moreover, the binary counter and gates of the present invention are less costly and occupy less space than do the components of high quality R.C. networks. It is, therefore, an object of the present invention to provide a paper currency validator with timing circuits which utilize a binary counter and gates to provide a number of individually different time periods.

BRIEF DESCRIPTION OF THE DRAWING

In the drawing,

FIG. 1 is a vertical section through one preferred embodiment of bill transport that is made in accordance with the principles and teachings of the present invention,

FIG. 2 is a diagrammatic view of a bill in position adjacent the magnetic heads of the bill transport of FIG. 1,

FIG. 3A diagrammatically shows part of the circuit of the paper currency validator of which the bill transport of FIG. 1 is a part,

FIG. 3B diagrammatically shows another part of that circuit,

FIG. 3C diagrammatically shows a further part of that circuit,

FIG. 4 is a detailed showing of the components in the BORDER sub-block of FIG. 3B,

FIG. 5 is a detailed showing of the components in the SPEED ADJUSTING sub-block of FIG. 3A,

FIG. 6 is a detailed showing of the components in the SPEED MAINTAINING sub-block of FIG. 3A,

FIG. 7 is a detailed showing of the components in the OVERLEVEL SENSING sub-block of FIG. 3A,

FIG. 8 is a detailed showing of the components in the MOTOR AND RELAY sub-block and in the CURRENT SENSING sub-block of FIG. 3A,

FIG. 9 is a detailed showing of the components in the upper of the FREQUENCY DETECTOR sub-blocks of FIG. 3C,

FIG. 10 is a timing chart, and

FIG. 11 shows an alternate threshold device for the BORDER sub-block of FIG. 3B.

DESCRIPTION OF BILL TRANSPORT

Referring to FIG. 1, the numeral 30 generally denotes one preferred embodiment of bill transport that is made in accordance with the principles and teachings of the present invention. The numeral 32 denotes a platform which extends outwardly from the front of the bill transport 30; and that platform will receive the leading edge of each bill which is to be tested by the paper currency validator of which that bill transport is a part. A flange 34 and a counterpart flange, not shown, of generally triangular configurations extend upwardly from the sides of the platform 32; and that platform has an upwardly inclined inner end 38 which merges into a platen 40. An elongated flange 42 and a counterpart flange, not shown, extend downwardly from the elongated sides of the platen 40. The numeral 45 denotes the trailing edge of the platen 40; and that trailing edge inclines downwardly and then terminates in a vertically directed lip, as shown by FIG. 1.

The numeral 62 denotes a headed pin which is secured to the flange 42 and which is adjacent the front of the bill transport 30. The numeral 65 denotes a short pivot which is secured to the flange 42 and which is spaced an appreciable distance to the right of the headed pin 62. The numeral 66 denotes a further headed pin which is supported by the flange 42 and which is spaced to the right of the pivot 65.

The numeral 70 denotes a leaf-type spring which is bent so the right-hand end thereof, not shown, inclines upwardly to bear against the under surface of the platen 40. That spring is bent to have a downwardly opening saddle, not shown, which rests upon the pivot 65, to have an elongated portion which inclines upwardly and to the left from that saddle, and to have a bifurcated left-hand end with fingers that define an upwardly opening saddle. The numerals 72 and 74 denote springs which can be identical to the spring 70; but the bifurcated ends of those springs extend to the right rather than to the left in FIG. 1. The downwardly opening saddle of spring 72 rests upon the headed pin 62; and hence that spring is adjacent the front of the platen 40. The downwardly opening saddle of the spring 74 rests upon the headed pin 66; and hence that spring is adjacent the trailing edge of that platen.

A short pivot 80 is supported by the upwardly opening saddle which is defined by the fingers at the bifurcated end of the spring 72; and that pivot rotatably supports a roller 82. A similar pivot 84 is supported by the upwardly opening saddle which is defined by the fingers at the bifurcated end of the spring 70; and that pivot rotatably supports a roller 86. A further similar pivot 88 is supported by the upwardly opening saddle which is defined by the fingers at the bifurcated end of the spring 74; and that pivot rotatably supports a roller 90.

The numeral 98 denotes an arm which has a hub that encircles the pivot 65. A pivot 100 is fixedly secured to the outer end of the arm 98; and that pivot rotatably supports a roller 102. A short pivot, not shown, which is the counterpart of pivot 65 is secured to the counterpart of flange 42 at a point to the left of pivot 65; and an arm, not shown, which is the counterpart of the arm 98 has the hub thereof encircling that short pivot. A pivot 112 is fixedly secured to the outer end of that arm; and that pivot rotatably supports a roller 114. Springs, not shown, encircle the short pivot 65 and its counterpart pivot; and those springs urge the rollers 102 and 114 upwardly relative to the platen 40.

The numeral 118 denotes an upper platen which normally is disposed in parallel relation with, and in close proximity to, the platen 40. The platen 118 has a downwardly directed flange 120 and a counterpart flange, not shown, at its elongated sides; and each of those flanges has a downwardly opening slot 122 adjacent the front end thereof. The numeral 124 denotes a semi-cylindrical leading edge of the platen 118; and that semi-cylindrical leading edge is disposed forwardly of the upwardly inclined rear portion 38 of the platform 32. The platen 118 has an upwardly inclined trailing edge 126, as shown by FIG. 1.

The numeral 140 denotes a cover for the bill transport 30; and that cover has a downwardly directed flange 142 and a counterpart flange, not shown, at the elongated sides thereof. The numeral 144 denotes a switch bracket which is secured to the cover 140; and that switch bracket holds a normally open, single-pole, single-throw switch 146 adjacent the front of the platen 118. The numeral 148 denotes a sturdy but thin actuator for the switch 146; and that actuator has a leading edge 150 and a trailing edge 152 which extend downwardly through slots, not shown, in the platens 118 and 40. The leading edge 150 is essentially straight, but the trailing edge 152 is convex. The configurations and inclinations of the leading and trailing edges 150 and 152, respectively, of actuator 148 enable the leading edge and trailing edge, respectively, of a bill to easily raise that actuator upwardly out of the slot in the platen 40. As a result, the switch actuator 148 permits relatively free movement of bills inwardly and outwardly of the bill transport 30.

The numeral 154 denotes a second switch bracket which is secured to the cover 140; and that switch bracket supports a normally open, single-pole, single-throw switch 156. The numeral 158 denotes a sturdy but thin actuator for the switch 156; and that actuator has a convex leading edge 159 and a straight trailing edge 161 which extend downwardly through slots, not shown, in the platens 118 and 40. The configurations and inclinations of the leading and trailing edges 159 and 161, respectively, of the switch actuator 158 enable the leading edge and trailing edge, respectively, of a bill to easily raise that actuator upwardly out of the appropriate slot in the platen 40. As a result, the switch actuator 158 permits relatively free movement of bills inwardly and outwardly of the bill transport 30.

The numeral 160 denotes a third switch bracket which is secured to the cover 140; and that switch bracket is adjacent the rear of that cover. That switch bracket supports a normally open, single-pole, single-throw switch 162; and that switch has an actuator 164 with a leading edge 166 and a trailing edge 168 which extend downwardly through slots, not shown, in the platens 118 and 40. The leading edge 166 is essentially straight; but the trailing edge 168 is generally convex and is quite short. That trailing edge normally is disposed an appreciable distance below the lower face of the platen 40. As a result, the trailing edge of a bill will not normally engage the edge 168 of the actuator 164 once that trailing edge has moved inwardly beyond that edge. If a person were to attempt to pull a bill outwardly of the bill transport 30, after the trailing edge of that bill had been moved inwardly beyond the edge 168 of actuator 164, the trailing edge of that bill would be intercepted by the inner surface of the leading edge 166 of that actuator. In that event, the actuator 164 would make it impossible for that person to recover that bill in intact form.

The numerals 188 and 190 denote pulleys which are mounted on short pivots, not shown, that are supported by the flange 42; and the numeral 194 denotes a pulley which is mounted on an elongated shaft 182 that is rotatably supported by bushings which are mounted in the flange 142 and in its counterpart flange. The pulleys 188, 190 and 194 accommodate an elongated endless belt 198; and the lower "run" of that belt is engaged by the upper portions of the rollers 82, 86 and 90. A worm wheel 200 is fixedly secured to the shaft 182; and a worm gear 202 meshes with that worm wheel. That worm gear is mounted on the output shaft 203 of a D.C. motor 562 which is indicated diagrammatically in FIG. 8 and which is enclosed by a motor housing 204 shown in FIG. 1. That motor housing extends upwardly from the cover 140; and it has its axis perpendicular to the central portion of that cover. The motor 562 is a reversible permanent magnet D.C. motor which drives an A.C. generator 560 by means of a connection 564. That A.C. generator is located within the motor housing 204; and that connection is a direct mechanical connection. In the said preferred embodiment of bill transport, the motor 562, the A.C. generator 560 and the connection 564 are parts of a type CYQM Motor With Integral Tachometer Generator which is marketed by the Barber Colman Company as model No. CYQM 23360-3. When the motor 562 is energized in the "forward" direction, it will directly drive the A.C. generator 560 in that direction, and it will drive the lower "runs" of the belt 198 and of its counterpart belt inwardly of the bill transport 30. When that motor is energized in the "reverse" direction, it will directly drive the A.C. generator 560 in that direction, and it will drive the lower "runs" of belt 198 and of its counterpart belt outwardly of that bill transport.

The numeral 206 denotes a mounting bracket which fixedly holds magnetic heads 208 and 210 in spaced-apart relation. Those magnetic heads are spaced both laterally and longitudinally of the elongated axis of the bill transport 30. As indicated particularly by FIG. 2, which looks downwardly past those magnetic heads at an outline that generally represents the black-ink face of an authentic U.S. 1 dollar bill 212, the air gaps of those magnetic heads will sense two laterally spaced, longitudinally extending paths.

The numeral 220 denotes an elongated pivot which has the opposite ends thereof secured to the rear portions of the flange 120 and of its counterpart flange, not shown, on the upper platen 118; and that pivot extends through aligned openings in the flange 42 and in the counterpart flange, not shown, on the lower platen 40. As a result, the pivot 220 enables the upper platen 118 -- and the cover 140 plus the various components which are mounted on that upper platen and on that cover -- to be rotated upwardly and away from the lower platen 40. Such rotation is desirable; because it permits ready and free access to the space between the lower platen 40 and the upper platen 118. However, the upper platen 118 will normally respond to its weight, to the weight of the cover 140, and to the weight of the components mounted on that upper platen and on that cover to urge the lower face of the lower "run" of the belt 198 into intimate engagement with the upper faces of the rollers 82, 86 and 90. The springs 70, 72 and 74 will yield slightly in response to the combined weights of the upper platen 118, of the cover 140, and of the components which are carried by that upper platen and by that cover; but those springs will hold the upper surfaces of the rollers 82, 86 and 90 above the upper surface of the lower platen 40. Those rollers and the rollers 102 and 114 are in register with openings, not shown, in that lower platen.

The bill transport 30 is essentially identical to the identically numbered bill transport in the said Fishel et al application, except that the magnetic head 210 has been shifted closer to the leading edge of the platen 118, and the arm 98 and its counterpart have been mounted on the short pivot 65 and its counterpart pivot instead of being mounted on the same elongated pivot. In the said preferred embodiment of bill transport, the air gaps of the magnetic heads 208 and 210 define parallel lines which are transverse of the longitudinal axis of the platen 118 and which are spaced apart one-half of an inch. The inner faces of the magnetic heads 208 and 210 are spaced apart one-sixteenth of an inch transversely of the longitudinal axis of the platen 118. Consequently, when the vertical centerline of the upper part of the engraved portrait of George washington on an authentic U.S. 1 dollar bill is in engagement with the air gap of the magnetic head 208, the lower left-hand quadrant of the background for that portrait will be in engagement with the air gap of the magnetic head 210, as indicated by FIG. 2.

DESCRIPTION OF THE CIRCUIT

FIGS. 3A-3C, which diagrammatically show the circuit of the preferred embodiment of paper currency validator provided by the present invention, include a number of blocks and sub-blocks. The numeral 230 in FIG. 3A denotes a START AND RUN LOGIC block which contains a three-input NAND gate 232. Conductors 766, 776 and 780 extend from a SWITCH LOGIC block in FIG. 3B to the three inputs of the NAND gate 232. A branched conductor 234 is connected to the output of NAND gate 232; and one branch of that conductor extends to the input of an inverter 238 within a VEND ENABLE LOGIC block 236. The output of that inverter is connected to the upper input of a two-input NAND gate 240 and to a conductor 241.

In the drawing and accompanying description the switches 146, 156 and 162 are switches which have movable and stationary contacts and which have actuators which respond to the leading and trailing edges of bills to move those movable contacts. However, if desired, photoelectric cells and other bill-sensing devices could be substituted for the switches 146, 156 and 162. Consequently, it will be recognized that the term "switch" as used herein includes photo cells and other bill-sensing devices.

A conductor 850 extends from a VALIDATING AND VENDING LOGIC block 784 in FIG. 3C to the lower input of NAND gate 240. The other branch of conductor 234 extends to the lower input of a two-input NAND gate 328 within a MOTOR REVERSE LOGIC block 286. The conductor 241 extends to the cathode of a diode 245; and the anode of that diode is connected to a source of regulated plus twelve volts D.C. by a resistor 247, to ground by a capacitor 249, and to the upper input of a NAND gate. A conductor 253 connects the output of that NAND gate to a SPEED MAINTAINING sub-block 358 within a MOTOR CONTROLLING block 354.

A branched conductor 242 is connected to the output of NAND gate 240; and one branch of that conductor extends to the upper input of aa two-input NAND gate 246 within a TIMER block 244. A branch of conductor 766 extends to the lower input of NAND gate 246. The output of NAND gate 246 is connected to the lower input of a two-input NAND gate 248; and a resistor 250 extends between the source of regulated plus twelve volts D.C. and the upper input of that NAND gate. The output of NAND gate 248 is connected to the "reset" input of a BINARY COUNTER 254; and the output of a PULSE GENERATOR 252 is connected to the "count" input of that BINARY COUNTER. The input of the PULSE GENERATOR 252 is connected to a source of sixty Hertz signals. Although different pulse generators could be used, a Schmitt trigger has been found to be quite useful as the PULSE GENERATOR 252; and it acts to steepen the leading edges and to flatten the tops of sine waves that are supplied to it by the source of sixty Hertz signals. Although different binary counters could be used, the RCA 4024 seven-stage binary counter has been found to be quite useful as the BINARY COUNTER 254. A conductor 256 extends from the binary four output terminal of the BINARY COUNTER 254 to the upper input of a three-input NAND gate 272 in a TIMER LOGIC block 262. A branched conductor 258 extends from the binary eight output terminal of the BINARY COUNTER 254 to the lower input of a two-input NAND gate 266, to the upper input of a three-input NAND gate 268, and to the middle input of the three-input NAND gate 272. A branched conductor 260 extends from the binary 32 output terminal of the BINARY COUNTER 254 to the middle input of NAND gate 268, to the upper input of a two-input NAND gate 270, and to the lower input of NAND gate 272. A branch of conductor 780 is connected to the lower input of NAND gate 270. A conductor 852 extends from the VALIDATING AND VENDING LOGIC block 784 in FIG. 3C to the lower input of NAND gate 268.

Another branch of conductor 242 extends to the input of an inverter 264 in the TIMER LOGIC block 262; and the output of that inverter is connected to the upper input of the NAND gate 266. A further branch of the conductor 242 extends to the lower input of NAND gate 251; and a still further branch of that conductor extends to the input of an inverter 762 in the SWITCH LOGIC block 738 in FIG. 3B. The remaining branch of conductor 242 extends to the lower inputs of NOR gates 838 and 840 in the VALIDATING AND VENDING LOGIC block 784 in FIG. 3C.

A conductor 278 extends from the output of NAND gate 266 to the second-uppermost inputs of four-input NAND gates 728 and 730 in an INHIBIT LOGIC block 718 in FIG. 3B. A conductor 280 extends from the output of NAND gate 268 to the upper input of a four-input NAND gate 326 in the MOTOR REVERSE LOGIC block 286. A conductor 282 extends from the output of NAND gate 270 to the second uppermost input of NAND gate 326. An inverter 274 has the input thereof connected to the output of NAND gate 272, and it has the output thereof connected to the anode of a diode 276. A conductor 284 connects the cathode of diode 276 to the upper input of a three-input NOR gate 295 in the MOTOR REVERSE LOGIC block 286.

The numerals 288, 290, 292 and 294 denote further three-input NOR gates within the MOTOR REVEERVE LOGIC block 286; and branches of conductor 776 extend to the upper inputs of NOR gates 288 and 292. Branches of conductor 780 extend to the middle input of NOR gate 290 and to the lower input of NOR gate 292. A branch of conductor 766 extends to the middle input of NOR gate 294. A conductor 764 extends from the SWITCH LOGIC block 738 to the upper inputs of NOR gates 290 and 294. A conductor 778 extends from that SWITCH LOGIC block to the middle input of NOR gate 292 and to the lower input of an OVERLEVEL SENSING sub-block 296. A branch of conductor 852 is connected to the lower input of NOR gate 288; and a conductor 768 extends from SWITCH LOGIC block 738 to the middle input of that NOR gate and to the lower input of NOR gate 294. A conductor 791 extends from the VALIDATING AND VENDING LOGIC block 784 to the upper input of the OVERLEVEL SENSING sub-block 296. A diode 298 has the anode thereof connected to the output of NAND gate 288, and has the cathode thereof connected to the upper input terminal of NOR gate 295 by the conductor 284. Similarly, a diode 300 has the anode thereof connected to the output of NAND gate 290, and has the cathode thereof connected to the upper input of NOR gate 295 by the conductor 284. A conductor 297 and the conductor 284 connect the output of the OVERLEVEL SENSING sub-block 296 to the upper input of NOR gate 295. The output of NOR gate 292 is directly connected to the middle input of NOR gate 295; and the output of NOR gate 294 is directly connected to the lower input of that NOR gate.

The numeral 302 denotes an NPN transistor in the MOTOR REVERSE LOGIC block 286; and a resistor 312 connects the connector of that transistor to the source of regulated plus twelve volts D.C. The emitter of that transistor is grounded; and the base of that transistor is connected to the junction of resistors 306 and 308 which coact with a thirteen volt Zener diode 304 to constitute a voltage divider between ground and a source of non-regulated plus 24 volts D.C. A capacitor 329 is connected between ground and the collector of transistor 302; and a resistor 310 is connected between ground and the conductor 284, and thus is connected between ground and the upper input of NOR gate 295.

An inverter 314 has the input thereof connected to the collector of transistor 302, and has the output thereof connected to the cathode of a diode 318; and a conductor 316 extends from that cathode to the uppermost inputs of the NAND gates 728 and 730 in the INHIBIT LOGIC block 718. The output of NOR gate 295 is directly connected to the cathode of a diode 320; and the anodes of diodes 318 and 320 are connected together and to the second lowermost input of NAND gate 326 by a conductor 324. A resistor 322 connects the conductor 324 to the source of regulated plus 12 volts D.C.

The output of the NAND gate 326 is connected to the input of a RELAY DRIVER 330, and also to the upper input of NAND gate 328. Although different relay drivers could be used, a simple transistor stage which responds to a 0 at the input thereof to provide a 1 at the output thereof and which responds to a 1 at the input thereof to provide a 0 at the output thereof is quite usable. A conductor 332 extends from the output of relay driver 330 to a MOTORR AND RELAY sub-block 360 within the MOTOR CONTROLLING block 354. The output of NAND gate 328 is directly connected to the lower input of NAND gate 326 and, by a cnductor 334, to the second-lowermost inputs of NAND gates 728 and 730 in the INHIBIT LOGIC block 718.

As shown particularly by FIG. 7, the OVERLEVEL SENSING sub-block 296 has a resistor 336 which connects the conductor 791 to the base of an NPN transistor 338. The emitter of that transistor is connected to the junction of resistors 350 and 352 which constitute a voltage divider that is connected between ground and the source of regulated plus twelve volts D.C. A iode 340 has the anode thereof connected to the conductor 778; and has the cathode thereof directly connected to the emitter of a PNP transistor 346 and, by series-connected resistors 342 and 344, to the collector of transistor 338. The junction between the resistors 342 and 344 is connected to the base of transistor 346. A resistor 348 is connected between the collector of transistor 346 and ground; and that collector also is connected to conductor 297.

Conductors 368 and 370 extend from the MOTOR AND RELAY sub-block 360 to a SPEED ADJUSTING sub-block 356. As shown particularly by FIG. 5, the latter sub-block includes a full wave diode bridge 376; and conductor 368 is connected to one of the A.C. terminals of that bridge, and the conductor 370 is connected to the other of those A.C. terminals. One of the D.C. terminals of that bridge is grounded, and the other of those D.C. terminals is connected to the base of an NPN transistor 378 by a resistor 380. A resistor 382 is connected between ground and the base of that transistor; and the emitter of that transistor is grounded. The collector of that transistor is connected to the source of regulated plus 12 volts D.C. by a resistor 384.

A capacitor 386 is connected between the collector of transistor 378 and terminal 2 of a MONOSTABLE MULTIVIBRATOR 392. Although different monostable multivibrators could be used, the NE 555V monostable multivibrator made by the Signetics corporation has been found to be very useful. A diode 388 has the anode thereof connected to the right-hand terminal of capacitor 386, and has the cathode thereof connected to the regulated source of plus 12 volts D.C.; and a resistor 390 is connected in parallel with that diode. Terminal 1 of the monostable multivibrator 392 is directedly connected to ground, terminal 8 is directly connected to the regulated source of plus 12 volts D.C., and terminals 6 and 7 are connected together and to a junction between a resistor 398 and a capacitor 396 which are connected between ground and that regulated source of plus 12 volts D.C. Terminal 5 of that monostable multivibrator is connected to ground by a capacitor 394; and terminal 4 is connected to ground by a capacitor 410. The latter terminal also is connected to the regulated source of plus 12 volts D.C. and to the upper terminal of a resistor 400. That resistor and a resistor 402 are connected in series between ground and the regulated source of plus 12 volts D.C. Terminal 3 of the monostable multivibrator 392 is connected to the base of an NPN transistor 414 by a resistor 412. The emitter of that transistor is directly connected to ground, and the collector of that transistor is connected to the junction between resistors 400 and 402. A resistor 404, a potentiometer 408 and a resistor 406 constitute a voltage divider which is connected between ground and the regulated source of plus 12 volts D.C.; and the movable contact of that potentiometer is connected to the inverting terminal of an amplifier 420. Although different amplifiers could be used, an MC 1741 Motorola amplifier has been found to be very useful. A resistor 416 is connected between the collector of transistor 414 and the non-inverting input of amplifier 420; and a capacitor 418 is connected between that non-inverting input and ground. One of the terminals of the amplifier 420 is directly connected to ground; and another of those terminals is directly connected to an un-regulated source of plus 24 volts D.C., and is connected to ground by a capacitor 422. A capacitor 424 is connected between the output and the inverting terminal of the amplifier 420; and a series-connected capacitor 426 and resistor 428 also are connected between that output and that inverting terminal.

A Zener diode 430, a resistor 432, and a conductor 364 connect the output of amplifier 420 to the collector of an NPN transistor 466, to the anode of a diode 470, and to the base of an NPN transistor 468 which are in the SPEED MAINTAINING sub-block 358 -- as shown by FIG. 6. The emitter of transistor 466 is directly connected to ground, the cathode of diode 470 is connected to ground by a resistor 472, and the emitter of transistor 468 is connected to ground by a resistor 479. A two-input NAND gate 434 has those inputs connected together to enable that NAND gate to act as an inverter; and those inputs are connected to the conductor 253. The output of that NAND gate is connected to the base of an NPN transistor 438 by a resistor 436. The emitter of that transistor is directly grounded, and the collector of that transistor is connected to the cathodes of diodes 442 and 444. A resistor 440 connects the anode of diode 442 to the regulated source of plus 12 volts D.C.; and the anode of diode 444 is directly connected to the upper inputs of two-input NAND gates 448 and 450, and is connected to the regulated source of plus 12 volts D.C. by a resistor 446. A resistor 452 and a capacitor 454 constitute a series RC circuit which is connected between ground and the regulated source of plus 12 volts D.C.; and the junction between that resistor and that capacitor is connected to the lower input of NAND gate 448. A diode 456 has the anode thereof connected to the output of NAND gate 448; and it has the cathode thereof connected to the lower input of NAND gate 450 by a resistor 462. A capacitor 458 and a resistor 460 constitute a parallel-connected RC circuit which is connected between ground and the cathode of diode 456. The output of NAND gate 450 is connected to the base of transistor 466 by a resistor 464. A resistor 478 connects the collector of transistor 468 to the cathode of a diode 476 and to the base of a PNP transistor 480. A resistor 474 connects the anode of diode 476 to the regulated source of plus 24 volts D.C.; and a resistor 484 connects the emitter of transistor 480 to that regulated source. Resistors 486 and 488 connect the collector of transistor 480 to a conductor 366 which extends to the MOTOR AND RELAY sub-block 360 of FIG. 8. The junction between those resistors is connected to the base of an NPN transistor 482; and the collector of that transistor is connected directly to the regulated source of plus 24 volts D.C., and the emitter of that transistor is directly connected to the conductor 366.

As shown particularly by FIG. 8, the conductor 366 is connected to a movable relay contact 492, to the cathode of a diode 496 and to one terminal of a capacitor 498. The anode of diode 496, the other terminal of capacitor 498, and a movable relay contact 494 are connected together and to a conductor 372 which extends to a CURRENT SENSING sub-block 362. The "forward" stationary relay contact 492 is connected to the upper terminal of motor 562, and the "reverse" stationary relay contact 492 is connected to the lower terminal of that motor. The "forward" stationary relay contact 494 is connected to the lower terminal of motor 562, and the "reverse" stationary relay contact 494 is connected to the upper terminal of that motor. The coil which controls the movable relay contacts 492 and 494 is denoted by the numeral 490; and one terminal of that coil is connected to the regulated source of plus 24 volts D.C., while the other terminal of that coil is connected to the conductor 332. One terminal of the A.C. generator 560 is connected to the conductor 370, while the other terminal of that A.C. generator is connected to the conductor 368.

The conductor 372 is connected to the base of an NPN transistor 500 by series-connected resistors 504 and 508. A resistor 502 is connected between ground and the junction between conductor 372 and resistor 504; and a resistor 506 is connected between ground and the junction between resistors 504 and 508. The emitter of transistor 500 is grounded; and the collector of that transistor is directly connected to the input of an inverter 512, and is connected to the regulated source of plus 12 volts D.C. by a resistor 510.

The output of the inverter 512 is connected to a conductor 374 which extends to the uppermost input of a four-input NOR gate 518 in a COUNT ENABLE block 514. One branch of conductor 776 is connected to the second lowermost input of that NOR gate, and one branch of conductor 780 is connected to the lowermost input of that NOR gate. A branch of conductor 778 is connected to the lower input of a "BORDER" sub-block 516, and a branch of conductor 791 is connected to the upper input of that sub-block. The output of that sub-block is connected to the second uppermost input of NOR gate 518 by a conductor 517. The output of that NOR gate is connected to the input of an inverter 520; and the output of that inverter is connected to the lower input of two-input NOR gates 800 and 802 in the VALIDATING AND VENDING LOGIC block 784 by a conductor 522.

As shown particularly in FIG. 4 the BORDER sub-block 516 has a resistor 684 which connects the conductor 791 to the base of an NPN transistor 682. Resistors 688 and 690 constitute a voltage divider connected between ground and the regulated source of plus 12 volts D.C.; and the junction between those resistors is connected to the emitter of transistor 682. A resistor 686 connects the collector of that transistor to the regulated source of plus 12 volts D.C. A resistor 692 connects the collector of transistor 682 to the upper inputs of two-input NANd gates 696 and 700. A capacitor 694 is connected between ground and the junction between resistor 692 and those upper inputs; and that capacitor will by-pass to ground any high frequency pulses, on conductor 791, such as transients and motor noise. The output of NAND gate 696 is connected to the lower input of NAND gate 700 and also to the upper input of a two-input NAND gate 698. The lower input of NAND gate 698 is connected to a branch of conductor 778. The output of NANd gate 698 is connected to the lower input of NANd gate 696, and also to the lower input of a two-input NOR gate 708. The anode of a diode 702 is connected to the output of NANd gate 700; and the cathode of that diode is connected to the interconnected inputs of a two-input NOR gate 704 which serves as an inverter. A resistor 710 and a capacitor 712 constitute a parallel-connected R.C. network connected between ground and the interconnected inputs of NOR gate 704. The output of NOR gate 704 is connected to the cathode of a diode 713; and the anode of that diode is connected to the upper input of a two-input NOR gate 706. A resistor 714 and a capacitor 716 constitute a series-connected R.C. circuit connected between ground and the source of regulated plus 12 volts D.C.; and the junction between that resistor and that capacitor is connected to the anode of diode 713, and to the upper input of NOR gate 706. The output of NOR gate 708 is connected to the lower input of NOR gate 706; and the output of NOR gate 706 is connected to the upper input of NOR gate 708 and also to the conductor 517.

The numeral 524 denotes a COUPLING block in FIG. 3B; and that block has terminals 526, 528 and 530 which are connectable to a dispensing machine such as a change-making machine. In one preferred embodiment of the present invention, the terminal 526 is connected to a circuit of a dispensing machine which can selectively indicate that dollar bills should not be accepted, and the terminal 530 is connected to a circuit in that dispensing machine which can selectively indicate that 5 dollar bills should not be accepted. The terminal 528 is connected to a common conductor from that dispensing machine. A resistor 532 is connected between the terminal 526 and the anode of a diode 536; and a resistor 534 is connected between the terminal 530 and the anode of a diode 538. The chathodes of the diodes 536 and 538 are connected together and to the common terminal 528. an opto-coupler 540 is connected in parallel with the diode 536 and an opto-coupler 542 is connected in parallel with the diode 538. The emitters of the light-sensitive elements in those opto-couplers are connected together and to ground. The collector of the light-sensitive element in opto-coupler 540 is directly connected to the cathode of a diode 548, and is connected to the source of regulated plus 12 volts D.C. by a resistor 544. The collector of the light sensitive element in the opto-coupler 542 is directly connected to the cathode of a diode 550, and is connected to the source of regulated plus 12 volts D.C. by a resistor 546. A resistor 552 and a capacitor 556 are connected in series between the source of regulated plus 12 volts D.C. and ground; and the junction between that resistor and that capacitor is connected to the anode of diode 548, and also to a conductor 566 which extends to the INHIBIT LOGIC block 718. A resistor 554 and a capacitor 558 are connected in series between the source of regulated 12 volts D.C. and ground; and the junction between that resistor and capacitor is connected to the anode of diode 550 and to a conductor 568 which extends to that INHIBIT LOGIC block.

The conductor 566 is connected to the upper input of a two-input NAND gate 720 and also to the input of an inverter 724. The conductor 568 is connected to the lower input of NAND gate 720, and also to the input of an inverter 726. The output of NAND gate 720 is connected to the input of an inverter 722; and the output of that inverter is connected to a conductor 732 which extends to the SWITCH LOGIC block 738. The output of inverter 724 is connected to the lowermost input of NAND gate 728; and the output of inverter 726 is connected to the lowermost input of NAND gate 730. The output of NAND gate 728 is connected to a conductor 736 which extends to the VALIDATING AND VENDING LOGIC block 784; and the output of NAND gate 730 is connected to a conductor 734 which also extends to that block.

The movable contacts of the switches 146, 156 and 162 are connected together and to ground, as shown by FIG. 3B. A resistor 740 connects the stationary contact of switch 146 to the source of regulated plus 12 volts D.C.; and a resistor 746 connects that stationary contact to the lower input of a three-input NOR gate 758. A capacitor 752 is connected between ground and the junction between resistor 746 and that lower input. A resistor 742 connects the stationary contact of switch 156 to the source of regulated plus 12 volts D.C.; and a resistor 748 connects that stationary contact to the conductor 766 and also to the input of an inverter 772. The output of that inverter is connected to the conductor 778. A capacitor 754 is connected between ground and the junction of resistor 748, conductor 766, and the input of inverter 772. A resistor 744 connects the stationary contact of switch 162 to the source of regulated plus 12 volts D.C.; and a resistor 750 connects that stationary contact to the lower input of a two-input NOR gate 760. A capacitor 756 is connected between ground and the junction between resistor 750 and that lower input. The inverter 762 has the output thereof connected to the upper input terminals of NOR gate 758 and 760; and the middle input terminal of NOR gate 758 is connected to the conductor 732. The output of NOR gate 758 is connected to conductor 764 and to the input of an inverter 770; and the output of that inverter is connected to conductor 776. The output of NOR gate 760 is connected to conductor 768 and to the input of an inverter 774; and the output of that inverter is connected to conductor 780.

A constant current diode 786 in FIG. 3C connects one terminal of the magnetic head 208 to the source of regulated plus 12 volts D.C. Although different constant current diodes could be used, a 1N5297 constant current diode has been found to be very useful. The other terminal of magnetic head 208 is connected to one terminal of magnetic head 210; and the other terminal of the latter magnetic head is connected to ground by a resistor 788. An amplifier 790 has one input terminal thereof connected to the junction between the cathode of constant current diode 786 and the upper terminal of magnetic head 208, and has the other terminal thereof connected to the junction between resistor 788 and the lower terminal of magnetic head 210. The output of amplifier 790 is connected to conductor 791. One branch of that conductor is connected to the input of a FREQUENCY DETECTOR sub-block 792, and another branch of that conductor is connected to the input of a FREQUENCY DETECTOR sub-block 794. As shown particularly by FIG. 9, the FREQUENCY DETECTOR sub-block 792 includes a phase locked loop 854. One very useful phase locked loop is the NE567V phase locked loop of the Signetics Corporation. A resistor 856 and a capacitor 862 connect the conductor 791 to terminal 3 of the phase locked loop 854. Oppositely polarized diodes 858 and 860 are connected between ground and the junction between resistor 856 and capacitor 862. A potentiometer 878 has one terminal thereof connected to pin 5 of the phase locked loop 854 and has the other terminal thereof connected to pin 6 of that phase locked loop by a fixed resistor 880. The movable contact of that potentiometer is connected to the junction between that potentiometer and that resistor to enable that potentiometer to serve as an adjustable resistor. A capacitor 882 is connected between ground and the junction between resistor 880 and pin 6 of the phase locked loop 854. A conductor 876 directly connects pin 7 of that phase locked loop to ground; and a conductor 864 connects pin 4 of that phase locked loop to a source of regulated plus 6 volts D.C. A capacitor 866 connects pin 2 of that phase locked loop to ground; and a conductor 795 is connected to pin 8 of that phase locked loop. A resistor 867 and a conductor 868 connect pin 1 of the phase locked loop to the source of regulated plus 6 volts D.C.; and a capacitor 870 connects that pin to ground. A resistor 872 and a capacitor 874 connect pin 1 to pin 8 of that phase locked loop.

The FREQUENCY DETECTOR 794 is identical to the FREQUENCY DETECTOR 792 in all respects other than the value of the resistor 880. Thus, in the said preferred embodiment of the present invention, each of the FREQUENCY DETECTOR sub-blocks 792 and 794 has a 2,200 ohm resistor 856, has 1N914 diodes 858 and 860, has a one-tenth microfarad capacitor 862, has a 22/100 of a microfarad capacitor 866, has a 10,000 ohm potentiometer 878, has a 68/1,000 of a microfarad capacitor 882, has a two and two-tenths microfarad capacitor 870, has a 100,000 ohm resistor 867, has a 100 ohm resistor 872, and has a 22/100 of a microfarad capacitor 874. The FREQUENCY DETECTOR sub-block 792 differs from the FREQUENCY DETECTOR sub-block 794 in having a 7,500 ohm resistor 880, whereas the latter FREQUENCY DETECTOR sub-block has a fourteen thousand seven hundred ohm resistor 880.

The conductor 795, which is connected to the output of FREQUENCY DETECTOR sub-block 792, is connected to the upper input of NOR gate 800; and a conductor 797, which is connected to the output of FREQUENCY DETECTOR sub-block 794, is connected to the upper input of NOR gate 802. A resistor 796 extends between conductor 795 and the source of regulated plug 12 volts D.C.; and a resistor 798 extends between the conductor 797 and that regulated source. The output of NOR gate 800 is connected to the "clock" input of a counter 804. While different counters could be used, an RCA 4015 Shift Register has been found to be very useful. The output of NOR gate 802 is connected to the "clock" input of a similar counter 806.

A stationary switch contact 812 and a stationary switch contact 818 are connected together and to the fourth output terminal of counter 804. Stationary switch contacts 814 and 816 are connected, respectively, to the second and third output terminals of that counter. A movable switch contact 808 and a movable switch contact 810 are "ganged" together; and those movable switch contacts coact with the stationary switch contacts 812, 814, 816 and 818 to constitute a two-pole, double-throw switch. In the position shown by FIg. 3C, movable contact 808 is in engagement with stationary contact 814 and movable contact 810 is in engagement with stationary contact 818. The movable contact 808 is connected to the upper input of a two-input NAND gate 834; and a conductor connects the third output terminal of counter 804 to the lower input of that NAND gate. The movable contact 810 is connected to the input of an inverter 819; and the output of that inverter is connected to the "data" input of the counter 804. The conductor 736 is connected to the "reset" terminal of the counter 804.

A stationary switch contact 824 and a stationary switch contact 830 are connected together and to the fourth output terminal of counter 806. Stationary switch contacts 826 and 828 are connected, respectively, to the second and third output terminals of that counter. A movable switch contact 820 is connected to the upper input of a two-input NAND gate 836; and a conductor extends from the third output terminal of that counter to the lower input of that NAND gate. A movable switch contact 822 is connected to the input of an inverter 832; and the output of that inverter is connected to the "data" input of counter 806. The movable contacts 820 and 822 coact with the stationary contacts 824, 826, 828 and 830 to define a two-pole, double-throw switch. In the position shown by FIG. 3C, movable contacts 820 and 822 are in engagement, respectively, with stationary contacts 826 and 830. The conductor 734 is connected to the "reset" terminal of the counter 806.

The output of NAND gate 834 is connected to the upper input of NOR gate 838, and also to the input of an inverter 844. The output of NAND gate 836 is connected to the upper input terminal of NOR gate 840, and also to the input of an inverter 842. The outputs of inverters 842 and 844 are connected, respectively, to the upper and lower inputs of an EXCLUSIVE OR gate 846. The output of that EXCLUSIVE OR gate is connected directly to the conductor 850 and to the input of an inverter 848; and the output of that inverter is connected to the conductor 852. The output of NOR gate 838 is connected to the input of a RELAY DRIVER 884; and the output of NOR gate 840 is connected to the input of a RELAY DRIVER 886. The RELAY DRIVERS 884 and 886 could be of different types; but, in the said one preferred embodiment those relay drivers are simple transistor stages which respond to 0's at the inputs thereof to provide 1's at the outputs thereof, and which respond to 1's at the inputs thereof to provide 0's at the outputs thereof. The output of RELAY DRIVER 884 is connected to one terminal of a relay coil 888; and the output of the RELAY DRIVER 886 is connected to one terminal of a relay coil 890. The other terminals of those relay coils are connected together and to the source of regulated plus 24 volts D.C. Those relay coils control contacts, not shown, in the dispensing machine, vending machine or other device with which the paper currency validator of the present invention is associated.

At-rest Condition of Paper Currency Validator: In the at-rest condition of the paper currency validator, each of the switches 146, 156 and 162 is open; and hence a binary 1 will appear at the lower inputs of NOR gates 758 and 760, on conductor 766, and at the input of inverter 772. This means that a binary 0 will appear on conductors 764, 768 and 778, and that a 1 will appear on conductors 776 and 780. The NAND gate 232 in the START AND RUN LOGIC block 230 in FIG. 3A will respond to the 1's at the inputs thereof to apply a 0 to the conductor 234; and the inverter 238 will respond to the resulting 0 at the input thereof to apply 1's to the upper input of NAND gate 240 and to the cathode of diode 245. The resulting back biasing of that diode will cause a 1 to appear at the upper input of NAND gate 251. The COUNTERS 804 and 806 in FIG. 3C will have 0's at the output terminals thereof; and NAND gates 834 and 836 will respond to the resulting 0's at the inputs thereof to apply 1's to the upper inputs of NOR gates 838 and 840 and to the inputs of inverters 842 and 844. The resulting application of 0's to both inputs of the EXCLUSIVE OR gate will cause that EXCLUSIVE OR gate to apply a 0 to conductor 850 and to the input of inverter 848; and that inverter will apply a 1 to conductor 852 -- and hence to the lower inputs of NAND gate 268 and of NOR gate 288.

The 0 on conductor 850 will cause NAND gate 240 in FIG. 3A to apply a 1 to conductor 242, and thus to the lower input of NAND gate 251. The 1's at both inputs of the latter NAND gate will cause that NAND gate to apply a 0 to conductor 253, and thus to the interconnected inputs of NAND gate 434 in the SPEED MAINTAINING sub-block of FIG. 6. The resulting 1 at the output of NAND gate 434 will be applied to the base of transistor 438, and will render that transistor conductive and cause it to apply a 0 to the cathode of diode 444. The resulting forward biasing of that diode will apply 0 to the upper inputs of NAND gates 448 and 450; and the resulting 1's at the outputs of those NAND gates will forward bias diode 456 and transistor 466. The source of regulated plus 12 volts D.C. will apply a 1 to the lower input of NAND gate 448. Capacitor 458 will respond to the forward biasing of diode 456 to charge up to a voltage close to 12 volts, and thereby will apply a 1 to the lower input of NAND gate 450. Transistor 466 will become conductive and will thereby apply a 0 to the base of transistor 468 -- to render the latter transistor non-conductive; and the resulting 1 at the base of transistor 480 will keep that transistor nonconductive. Consequently, a 0 will appear at the base of transistor 482 to render that transistor non-conductive; and hence current will not flow through conductor 366 and motor 562. As a result, that motor and the movable parts of the bill transport will remain at rest.

The constant current diode 786 in FIG. 3C will permit a fixed value of direct current to flow through the serially connected magnetic heads 208 and 210, and thereby will provide a D.C. bias in those heads. However, in the at-rest condition of the paper currency validator, those magnetic heads and the amplifier 790 will cause a 0 to appear on conductor 791. The transistor 338 in the OVERLEVEL SENSING sub-block 296 of FIG. 7 will be kept non-conductive by the 0 at the base thereof, and hence transistor 346 also will be kept non-conductive. As a result, the collector of transistor 346 will permit 0 to appear on conductor 297, and hence at the upper input of NOR gate 295.

The 0 on conductor 791 also will be applied to the inputs of FREQUENCY DETECTORS 792 and 794; and those FREQUENCY DETECTORS will respond to those 0's to permit 1's to appear at the outputs thereof. As a result 1 will appear at the upper input of each NOR gate 800 and 802.

The 1 on conductor 242 also will be applied to the input of inverter 264 -- with a consequent application of a 0 to the upper input of NAND gate 266. In addition, the 1 on conductor 242 will be applied to the inverter 762 in FIG. 3B -- with consequent application of 0's to the upper inputs of NOR gates 758 and 760, and to the lower inputs of NOR gates 838 and 840 in FIG. 3C; and those NOR gates will respond to that 1 or to the 1's which the NAND gates 834 and 836 apply to the lower inputs thereof to apply 0's to the inputs of RELAY DRIVERS 884 and 886. Those RELAY DRIVERS will apply 1's to the left-hand terminals of relay coils 888 and 890; and hence those relay coils will remain unenergized.

The PULSE GENERATOR 252 in FIG. 3A will be applying steep-sided, flat-topped pulses to the "count" terminal of the BINARY COUNTER 254 at a frequency of 60 Hertz; but NAND gate 246 will respond to the 1 on conductor 766 and to the 1 on conductor 242 to apply a 0 to the lower input of NAND gate 248. Although the source of regulated plus 12 volts applies a 1 to the upper input of NAND gate 248, the 0 at the lower input of that NAND gate will cause that NAND gate to apply a 1 to the "reset" terminal of BINARY COUNTER 254. As long as 1 is applied to that "reset" terminal, 0 will appear on all of the conductors 256, 258 and 260; and hence at the lower input of NAND gate 266, at the upper and middle inputs of NAND gate 268, at the upper input of NAND gate 270, and at all of the inputs of NAND gate 272. Those NAND gates will respond to those 0's to develop 1's at the outputs thereof. Inverter 274 will respond to the 1 at the output of NAND gate 272 to apply a 0 to the anode of diode 276--thereby back biasing that diode, and thus permitting 0 to appear on conductor 284 and hence at the upper input of NOR gate 295. The 1 on conductor 776 and the 1 on conductor 780 will cause NOR gates 288 and 290 to apply 0 to the anodes of diodes 298 and 300 -- thereby back-biasing those diodes, and thus permitting 0 to appear on conductor 284 and hence at the upper input of NOR gate 295. The 1 on conductor 776 and the 1 on conductor 766 will cause the NOR gates 292 and 294 to apply 0's to the middle and lower inputs of NOR gate 295; and hence that NOR gate will apply a 1 to the cathode of diode 320 -- with consequent back-biasing of that diode and the resulting application of a 1 to the second lowermost input of NAND gate 326. The transistor 302 will be conductive, and hence will be applying 0 to the input of inverter 314; and that inverter will apply a 1 to the cathode of diode 312 -- with consequent back-biasing of that diode and a resulting uninterrupted application of a 1 to the second lowermost input of NAND gate 326.

The 0 on conductor 234 will cause NAND gate 328 in the MOTOR REVERSE LOGIC block 286 in FIG. 3A to apply a 1 to the lowermost input of NAND gate 326; and the 1's at the outputs of NAND gates 268 and 270 will be applied to the uppermost and second uppermost inputs of NAND gate 326. As a result, that NAND gate will apply a 0 to the input of RELAY DRIVER 330 -- with the consequent application of a 1 to the left-hand end of relay coil 490 in FIG. 8 -- causing that coil to remain de-energized and to permit the movable relay contacts 492 and 494 to remain in their "forward" positions. NAND gate 326 also will apply a 0 to the upper input of NAND gate 328.

The dispensing machine, with which the paper currency validator is associated, will be applying 1's to the terminals 526 and 530 of the COUPLING block 524 in FIG. 3B; and hence the light-emitting diodes within the opto-couplers 540 and 542 will be emitting light. The light-sensitive elements of those opto-couplers will respond to that light to be conductive, and hence 0 will be applied to the cathodes of the diodes 548 and 550. The resulting forward biasing of those diodes will cause 0 to be applied to the upper and lower inputs of NAND gate 720 and also to the inputs of inverters 724 and 726. Those inverters will apply 1's to the lowermost inputs of NAND gates 728 and 730. The 1 at the output of NAND gate 266 of the TIMER LOGIC block 262 in FIG. 3A will appear at the second uppermost inputs of NAND gates 728 and 730, the 1 at the output of NAND gate 328 in the MOTOR REVERSE LOGIC block 286 in FIG. 3A will appear at the second lowermost inputs of NAND gates 728 and 730, and the 1 at the output of inverter 314 in that block will appear at the uppermost inputs of NAND gates 728 and 730. As a result 0's will appear at the outputs of those NAND gates, and hence at the "reset" terminals of COUNTERS 804 and 806 in the VALIDATING AND VENDING LOGIC block 784 in FIG. 3C. The 1 at the output of NAND gate 720 will cause inverter 722 to apply a 0 to the middle input of NOR gate 758.

The 0 on conductor 791 will be applied to the base of transistor 682 in the BORDER sub-block 516 in FIG. 4; and the resulting non-conductive state of that transistor will enable 1's to appear at the upper inputs of NAND gates 696 and 700. The 0 on conductor 778 will be applied to the lower input of NAND gate 698; with a consequent 1 at the output of that NAND gate and hence at the lower inputs of NAND gate 696 and of NOR gate 708. That NOR gate will apply a 0 to the lower input of NAND gate 706. NAND gate 696 will apply a 0 to the upper input of NAND gate 698, and also to the lower input of NAND gate 700; and the resulting 1 at the output of the latter NAND gate will forward bias diode 702 and thereby charge capacitor 712 and apply a 1 to the interconnected inputs of NOR gate 704. That NOR gate will apply a 0 to the cathode of diode 713 to forward bias that diode; and hence capacitor 716 will be discharged, and NOR gate 706 will have 0's at both inputs thereof, and thus will apply a 1 to the upper input of NOR gate 708 and also to conductor 517. That conductor will apply that 1 to the second uppermost input of NOR gate 518 and will thereby cause that NOR gate to apply a 0 to the input of inverter 520 -- with consequent application of a 1 to the lower inputs of NOR gates 800 and 802 in the VALIDATION AND VENDING LOGIC block 784 in FIG. 3C.

The 1 on conductor 776 will be applied to the second lowermost input of NOR gate 518, the 0 on conductor 764 will be applied to the upper inputs of NOR gates 290 and 294, the 0 on conductor 768 will be applied to the middle input of NOR gate 288 and to the lower input of NOR gate 294, and the 0 on conductor 778 will be applied to the middle input of NOR gate 292. The 1 on conductor 780 will be applied to the lower inputs of NOR gates 292 and 518 and of NAND gate 270, and the 0 on conductor 850 will be applied to the lower input of NOR gate 290. The CURRENT SENSING sub-block 362 will be applying a 1 to the uppermost input of NOR gate 518.

Operation of Paper Currency Validator by Authentic U.S. 1 Dollar Bill: If an authentic U.S. 1 dollar bill is disposed adjacent the platform 32 of the bill transport 30 of FIG. 1 so the black-ink face thereof is up and so the bottom of the portrait of George Washington is close to the flange 142 on the cover 140, the upper portion of the portrait background will be in register with the magnetic head 208 and the lower portion of that portrait background will be in register with the magnetic head 210, as indicated by FIG. 2. If the leading edge of that bill is moved far enough inwardly of that bill transport, it will cause the actuator 148 of switch 146 to move far enough to close that switch; and, thereupon, the 1 at the lower input of NOR gate 758 in the SWITCH LOGIC block 738 will change to 0. Immediately, the output of that NOR gate will change to 1 -- with a consequent 1 on conductor 764 and a consequent 0 on conductor 776. The resulting 1 at the upper input of NOR gate 294 will not be effective at this time because the 1 at the middle input of that NOR gate had been maintaining 0 at the output of that NOR gate. Similarly, the resulting 1 at the upper input of NOR gate 290 will not be effective at this time because the 1 at the middle input of that NOR gate had been keeping 0 at the output of that NOR gate. The resulting 0 at the second lowermost input of NOR gate 518 will not be significant at this time because the 1's at the second uppermost and bottom inputs will be maintaining 0 at the output of that NOR gate. The resulting 0 at the upper input of NOR gate 292 will not be significant at this time because the 1 at the lower input will be maintaining a 0 at the output of that NOR gate. Similarly, the resulting 0 at the upper input of NOR gate 288 will not be significant at this time because the 1 at the lower input will be maintaining a 0 at the output of that NOR gate. However, the resulting 0 at the upper input of NAND gate 232 will cause a 1 to appear at the output of that NAND gate and hence on conductor 234. The resulting application of 1 to the lower input of NAND gate 328 will not be significant at this time because the 0 at the upper input of that NAND gate will maintain 1 at the output of that NAND gate. However, the application of 1 to the input of inverter 238 in the VEND ENABLE LOGIC block 236 will cause that inverter to apply a 0 to the cathode of diode 245 and to the upper input of NAND gate 240. The 0 at the upper input of that NAND gate will not change the output of that NAND gate because conductor 850 has been applying a 0 to the lower input of that NAND gate; but the 0 at the cathode of diode 245 will forward bias that diode, and will thereby apply a 0 to the upper input of NAND gate 251. The resulting application of 1 to the interconnected inputs of NAND gate 434 in the SPEED MAINTAINING sub-block 358 of the MOTOR CONTROLLING block 354 will cause that NAND gate to apply 0 to the base of transistor 438, thereby rendering that transistor non-conductive. The resulting 1 at the cathode of diode 444 will back-bias that diode, and hence will enable the source of regulated plus twelve volts D.C. to apply 1's to the upper inputs of NAND gates 448 and 450. The resulting zero at the output of NAND gate 448 will back-bias diode 456, and thereby permit capacitor 458 to start discharging through resistor 460. However, that capacitor normally requires about eighteen seconds to discharge; and, during that length of time, it will continue to apply a 1 to the lower input of NAND gate 450. The 1 at the upper input of NAND gate 450 will cause that NAND gate to apply a 0 to the base of transistor 466, thereby rendering that transistor non-conductive. At such time, current will flow from the output of amplifier 420 in the SPEED ADJUSTING sub-block 356 of the MOTOR CONTROLLING block 354 via Zener diode 430, resistor 432, conductor 364, the base-emitter circuit of transistor 468 in SPEED MAINTAINING sub-block 358, and resistor 479 to ground; and that flow of current will render that transistor conductive. The resulting drop in the voltage at the junction of diode 476 and resistor 478 in that sub-block will render transistor 480 conductive; and, thereupon, current will flow through the base-emitter circuit of transistor 482 and render that transistor conductive. At such time, current will flow from the source of regulated plus 24 volts D.C. via transistor 482, conductor 366, the movable and left-hand relay contacts 492 in the MOTOR AND RELAY sub-block 360, motor 562, the left-hand and movable relay contacts 494, conductor 372, and in part to ground through resistor 502 in the CURRENT SENSING sub-block 362 and in part to ground through resistors 504 and 506. The motor 562 will start rotating in the "forward" direction, and the output shaft 203 thereof will rotate worm gear 202, worm wheel 200, and shaft 182; and the belt 198 and its counterpart belt will move the lower "runs" thereof to the right in FIG. 1, and will thereby move the bill inwardly of the bill transport. The motor 562 will drive those belts, and hence each inserted bill, at the rate of ten inches per second.

After the leading edge of the bill has been moved approximately one-half of an inch further inwardly of the bill transport by the belt 198 and its counterpart, the actuator 158 of the switch 156 will have been moved far enough to close that switch. Thereupon, 0 will appear on conductor 766 and 1 will appear on conductor 778. The resulting 0 at the middle input of NAND gate 232 in the START AND RUN LOGIC block 230 will not be significant at this time, because switch 146 remains closed and thereby maintains 1 at the output of that NAND gate. Similarly, the resulting 0 at the middle input of NOR gate 294 will not be significant at this time, because a 1 appears at the upper input of that NOR gate. However, the 0 at the lower input of NAND gate 246 will change the output of that NAND gate to 1, and thereby will cause NAND gate 248 to remove the 1 from the reset input of BINARY COUNTER 254; and, thereupon, that counter will begin to count the pulses from the PULSE GENERATOR 252.

The application of a 1 to the middle input of NOR gate 292 is not significant at this time bacause the 1 at the bottom input of that NOR gate is maintaining 0 at the output of that NOR gate. The application of a 1 to the anode of the diode 340 in the OVERLEVEL SENSING sub-block 296 of FIG. 7 will forward bias that diode; but the 0 at the base of transistor 338 will keep that transistor non-conductive, and will thereby act to keep transistor 346 non-conductive. Consequently, 0 will continue to appear at the output of that OVERLEVEL SENSING sub-block. The application of 1 to the lower input of NAND gate 698 in the Border sub-block 516 of FIG. 4 will not be effective at this time, because the NAND gate 696 will continue to apply 0 to the upper input of NAND gate 698. Consequently, the motor 562 will cause belt 198 and its counterpart to continue to move the bill inwardly of the paper currency validator, and the BINARY COUNTER 254 will begin counting.

During each operation of the paper currency validator, a number of events must occur within closely controlled, individually different time periods or the motor 562 will reverse and will cause the belt 198 and its counterpart to move the inserted bill back out through the front of the bill transport. For example, the switch 162 must close within 535 milliseconds after the switch 156 is closed, a validation signal must be developed within 668 milliseconds after switch 156 is closed, and switch 156 must re-open within 735 milliseconds after it is closed. Also, a time period of 134 milliseconds must have been developed by the time switch 162 re-opens if a validation signal is present. Those various time periods are established by the TIMER block 244 and by the TIMER LOGIC block 262.

The BINARY COUNTER 254 in TIMER block 244 will apply a 1 to conductor 256 whenever the total count therein is 4 through 7, 12 through 15, 20 through 23, 28 through 31, 36 through 39, and 44. That counter will apply a 1 to conductor 258 whenever the total count therein is 8 through 15, 24 through 31, and 40 through 44; and it will apply a 1 to conductor 260 whenever the total count therein is 32 through 44.

The BINARY COUNTER 254 will increase the total count therein each time it senses the negative-going edge of a pulse from the PULSE GENERATOR 252; and it will receive such pulses at the rate of one every 16 7/10 milliseconds. Approximately 67 milliseconds after the switch 156 is closed, a 1 will appear on conductor 256 and will be applied to the upper input of NAND gate 272; but that 1 will not have any immediate effect because conductors 258 and 260 will continue to apply 0's to the middle and lower inputs of that NAND gate. Approximately 134 milliseconds after switch 156 closes, the 1 on conductor 256 will change back to 0 and the 0 on conductor 258 will change to 1. The resulting 1 at the lower input of NAND gate 266 is not significant at this time because inverter 264 continues to apply a 0 to the upper input of that NAND gate. The resulting 1 at the upper input of NAND gate 268 is not significant at this time because conductor 260 continues to apply a 0 to the middle input of that NAND gate. The resulting 1 at the middle input of NAND gate 272 is not significant at this time because conductor 256 is applying a 0 to the upper input, and because conductor 260 is applying a 0 to the lower input, of that NAND gate.

Approximately 140 milliseconds after the switch 156 closed, the leading edge of the leading engraved border on the black-ink face of the bill will reach, and will start to move past, the air gap of the magnetic head 208. Thereupon, that magnetic head will apply pulses to the amplifier 790; and that amplifier will supply amplified pulses to the conductor 791.

Those amplified pulses will not have a frequency to which either of the FREQUENCY DETECTORS 792 and 794 is intended to respond; and hence those amplified pulses will not affect the 1's at the outputs of those FREQUENCY DETECTORS. Those amplified pulses will be applied to the base of transistor 338 in the OVERLEVEL SENSING sub-block 296 of FIG. 7; but those amplified pulses will not have sufficient amplitude to render the transistor 338 conductive. Consequently, that OVERLEVEL SENSING sub-block will continue to permit 0 to appear on conductor 297. Those amplified pulses also will be applied to the base of transistor 682 in the BORDER sub-block 516 of FIG. 4; and the negative-going portions of those amplified pulses will make that transistor non-conductive, but the positive-going portions of those amplified pulses will render that transistor conductive. As a result, during the time period when the air gap of magnetic head 208 is sensing the leading border of the bill, the upper inputs of NAND gates 696 and 700 will "see" a succession of alternating 0's and 1's.

The first 0 which is applied to the upper input of NAND gate 696 will make the output of that NAND gate a 1; and NAND gate 698 will respond to the resulting 1 at the upper input thereof and to the 1 which conductor 778 applies to the lower input thereof to apply a continuous 0 to the lower inputs of NOR gate 708 and of NAND gate 696. The NAND gates 696 and 698 thus act as an electronic "latch" which will maintain 0 at the lower input of NOR gate 708 and 1 at the lower input of NAND gate 700. The latter NAND gate will, in this way, be able to respond to the succession of alternating 0's and 1's at the upper input thereof to apply a succession of 1's and 0's to the anode of diode 702. Each 1 at that anode will forward-bias that diode and permit capacitor 712 to become charged; and each 0 at that anode will back-bias that diode and permit that capacitor to start discharging through resistor 710. However, the time constant of the RC network constituted by that capacitor and that resistor is about 60 milliseconds; and hence the rapidly-recurring forward-biasing of diode 702, in response to the amplified pulses from amplifier 790, will enable the charge on capacitor 712 to keep a 1 at the interconnected inputs of NOR gate 704. The resulting 0 at the output of that NOR gate will forward-bias the diode 713, thereby keeping capacitor 716 discharged and thereby applying a 0 at the upper input of NOR gate 706. The latter NOR gate will respond to the 0 at the lower input thereof, which has been maintained by the NOR gate 708, to apply a continuous 1 to the upper input of NOR gate 708 and to conductor 517. All of this means that as long as the leading border of the bill is in engagement with the air gap of the magnetic head 208, the capacitor 712 will maintain a 1 at the interconnected inputs of NOR gate 704.

The leading edge of the leading border on the black-ink face of the inserted bill will move into engagement with the air gap of the magnetic head 210 almost immediately after the trailing edge of that border moves beyond the air gap of the magnetic head 208; and the resulting amplified pulses from amplifier 790 will forward-bias and back-bias diode 702 in rapid succession. As a result, until the trailing edge of the leading border moves beyond the air gap of the magnetic head 210, the capacitor 712 will remain essentially fully charged, and thus will maintain a 1 at the interconnected inputs of NOR gate 704. In the preferred embodiment of the present invention, the magnetic heads 208 and 210 will respond to the leading border on the bill to cause the amplifier 790 to apply amplified pulses to the transistor 682 for approximately 90 milliseconds; and, during those 90 milliseconds, the voltage at the upper terminal of capacitor 712 will remain close to 12 volts.

Approximately 201 milliseconds after the switch 156 closed, and hence while the leading border of the bill was in engagement with the air gap of magnetic head 210, BINARY COUNTER 254 applied 1's to conductors 256 and 258. However, because conductor 260 was still applying 0's to the middle input of NAND gate 268 and to the lower input of NAND gate 272, and because conductor 242 was applying a 1 to the input of inverter 264 and thus was causing that inverter to apply a 0 to the upper input of NAND gate 266, the 1's on conductors 256 and 258 were not significant at that time.

As soon as the trailing edge of the leading border on the black-ink face of the bill moves beyond the air gap of magnetic head 210, the capacitor 712 will start discharging through resistor 710. About 60 milliseconds later, the charge on that capacitor will have dissipated through that resistor to the point where the 1 at the interconnected inputs of NOR gate 704 becomes a 0. At such time, a 1 will appear at the output of that NOR gate; and that 1 will back-bias diode 713. Thereupon, capacitor 716 will start to charge; but the time constant of the RC network, constituted by that capacitor and by resistor 714, is about 30 milliseconds. Consequently, a 0 will continue to appear at the upper input of NOR gate 706 for a total of about 90 milliseconds after the trailing edge of the leading border moves out of engagement with the air gap of the magnetic head 210; and then that 0 will change to a 1.

Approximately 70 milliseconds after the trailing edge of the leading border moves out of engagement with the air gap of the magnetic head 210, and hence approximately 20 milliseconds before the 1 on conductor 517 can become a 0, the leading edge of the bill will cause the actuator 164 of the switch 162 to move far enough to close that switch. In the said preferred embodiment of the present invention, the closing of switch 162 occurs approximately 300 milliseconds after the closing of switch 156. The resulting 0 at the lower input of NOR gate 760 will coact with the 0 at the upper input of that NOR gate to apply a 1 to conductor 768 and to the input of inverter 774 -- with a consequent application of 0 to conductor 780. The 1 which will appear at the middle input of NOR gate 288 will not be significant at this time because conductor 852 is applying a 1 to the lower input of that NOR gate. Similarly, the resulting 1 at the lower input of NOR gate 294 is not significant at this time because conductor 764 is applying a 1 to the upper input of that NOR gate. The resulting 0 at the lower input of NAND gate 232 is not significant to this time because conductors 766 and 776 are applying 0's to the upper and middle inputs of that NAND gate; and the resulting 0 at the lower input of NAND gate 270 is not significant at this time because conductor 260 is applying a 0 to the upper input of that NAND gate. The resulting 0 at the middle input of NOR gate 290 is not significant at this time because conductor 764 is applying a 1 to the upper input of that NOR gate; and the resulting 0 at the lower input of NOR gate 292 is not significant at this time because conductor 778 is applying a 1 to the middle input of that NOR gate. The resulting 0 at the lowermost input of NOR gate 518 is not significant at this time because conductor 517, which extends from the BORDER sub-block 516, is applying a 1 to the second uppermost input of that NOR gate.

Approximately 20 milliseconds after switch 162 closed, and hence approximately 320 milliseconds after switch 156 closed, the charge on capacitor 716 in the BORDER sub-block 516 of FIG. 4 will increase to a value at which the 0 at the upper input of NOR gate 706 will change to a 1. The resulting 0 on conductor 517 will be applied to the upper input of NOR gate 708 and to the second uppermost input of NOR gate 518. The 0 at the second uppermost input of NOR gate 518 will coact with the 0's at all of the other inputs of that NOR gate to cause that NOR gate to apply a 1 to the input of inverter 520; and the resulting 0 at the output of that inverter will be applied to the lower inputs of NOR gates 800 and 802. However, the outputs of those NOR gates will remain 0 because 1's appear at the outputs of the FREQUENCY DETECTORS 792 and 794. The 0 at the upper input of NOR gate 708 will coact with the 0 at the lower input of that NOR gate to apply a 1 to the lower input of NOR gate 706. Thereupon those NOR gates will act as an electronic "latch" which will maintain a continuous 0 on conductor 517, and hence at the second uppermost input of NOR gate 518, as long as switch 156 remains closed and keeps a 1 on conductor 778, and hence at the lower input of NAND gate 698.

Approximately 34 milliseconds after switch 162 closed, and hence approximately 334 milliseconds after switch 156 closed, BINARY COUNTER 254 will again apply a 1 to conductor 256. However, that 1 will not be significant at this time because conductors 258 and 260 are applying 0's to the middle and lower inputs of NAND gate 272.

Approximately 60 milliseconds after switch 162 closed, and hence approximately 360 milliseconds after switch 156 closed, the vertical grid lines in the leading half of the upper portion of the portrait background will engage and start moving past the air gap of the magnetic head 208. That magnetic head will respond to those vertical grid lines to develop pulses, and amplifier 790 will amplify those pulses and apply them to conductor 791. The base of transistor 338 in the OVERLEVEL SENSING sub-block 296 of FIG. 7 will receive those amplified pulses; but the amplitudes of those amplified pulses will not be great enough to cause that transistor to become conductive. Consequently, that OVERLEVEL SENSING sub-block will continue to supply a 0 to conductor 297. Those amplified pulses also will be applied to the base of transistor 682 in the BORDER sub-block 516 of FIG. 4; and that sub-block will respond to those amplified pulses to charge capacitor 712 and to forward bias diode 713, and thereby apply a 0 to the upper input of NOR gate 706. However, because that NOR gate and NOR gate 708 are acting as an electronic latch which maintains a continuous 0 on conductor 517, the amplified pulses which are applied to the BORDER sub-block 516 can not change the 0 on conductor 517, and hence can not cause a change in the 0's at the lower inputs of NOR gates 800 and 802 in FIG. 3C.

The amplified pulses from amplifier 790 will be applied to the inputs of FREQUENCY DETECTORS 792 and 794; and the back-to-back diodes 858 and 860 in the former FREQUENCY DETECTOR and the counterpart back-to-back diodes, not shown, in the latter FREQUENCY DETECTOR will limit the values of the amplified pulses that are applied to terminal 3 of the phase locked loop 854 in the former FREQUENCY DETECTOR and to terminal 3 of the counterpart phase locked loop in the latter FREQUENCY DETECTOR. The phase locked loop 854 is set to respond to the signals which are developed by the magnetic heads 208 and 210 when the vertical grid lines of an authentic U.S. 1 dollar bill engage the air gaps of those magnetic heads while the lower "runs" of the belt 198 and its counterpart are moving an inserted bill at the rate of 10 inches per second; and the phase locked loop in FREQUENCY DETECTOR 794 is set to respond to the signals which are developed by the magnetic heads 208 and 210 when the vertical grid lines of an authentic U.S. 5 dollar bill engage the air gaps of those magnetic heads while the lower "runs" of the belt 198 and its counterpart are moving an inserted bill at the rate of 10 inches per second.

The oscillator of the phase locked loop 854 will tend to shift its center frequency to match the frequency of the amplified pulses which are applied to terminal 3 thereof; but the values of capacitors 866, 870 and 874 and of resistor 872 limit the shifting of that center frequency to plus or minus 5 percent of that center frequency. As a result, that phase locked loop establishes a desirably narrow pass band that will enable it to respond to amplified pulses which the magnetic heads 208 and 210 generate in response to an authentic U.S. 1 dollar bill but that will enable it to be unresponsive to amplified pulses which the magnetic heads 208 and 210 generate in response to a spurious 1 dollar bill. As the oscillator of the phase locked loop 854 "locks on" the frequency of the amplified pulses applied to the terminal 3, the 1 on conductor 795 will change to a 0; and hence NOR gate 800 will change the 0 at the output thereof to a 1 and will apply that 1 to the clock input of COUNTER 804. Inverter 819 will be responding to the 0 at output terminal 4 of that COUNTER to apply a 1 to the data input terminal of that COUNTER; and hence the 1 at the clock input of that COUNTER will cause that COUNTER to develop a 1 at output terminal 1 thereof. However, because that output terminal is not connected to anything, the development of the 1 at that output terminal is not significant. As long as the oscillator of the phase locked loop 856 remains "locked on" the frequency of the amplified pulses applied to the terminal 3, the 1 will continue to appear at the output of NOR gate 800 and hence at the clock input of COUNTER 804. However, when the vertical grid lines in the leading half of the upper portion of the portrait background move beyond the air gap of magnetic head 208, as they will do approximately 374 milliseconds after switch 156 closed, the 0 at the output of that phase locked loop will be changed back to a 1. Thereupon, the 1 which NOR gate 800 was applying to the clock input of COUNTER 804 will be changed to a 0.

Approximately 401 milliseconds after switch 156 closed, BINARY COUNTER 254 will again apply a 1 to conductor 258. However that 1 will be unable to change the output of any of the NAND gates 266, 268 and 272, because each of those NAND gates has a 0 at one of the inputs thereof.

Approximately 406 milliseconds after switch 156 closed, the vertical grid lines in the leading half of the lower portion of the portrait background will move into engagement with the air gap of the magnetic head 210. Neither the OVERLEVEL SENSING sub-block 296 nor the BORDER sub-block 516 will change the output thereof in response to the resulting amplified pulses from amplifier 790. However, the FREQUENCY DETECTOR 792 will respond to those amplified pulses, in essentially the same manner in which it responded to the amplified pulses corresponding to the leading half of the upper portion of that portrait background, to again cause NOR gate 800 to apply a 1 to the clock input of COUNTER 804. Inverter 819 will be responding to the 0 at output terminal 4 of that COUNTER to apply a 1 to the data input terminal of that COUNTER; and hence the 1 at the clock input of that COUNTER will cause that COUNTER to develop a 1 at output terminal 1 thereof. That 1 at that output terminal will not be significant because that output terminal is not connected to anything, and the 1 which is developed at output terminal 2 of that COUNTER is not significant at this time because NAND gate 834 will have a 0 at the lower input thereof -- and hence will continue to apply a 1 to the upper input of NOR gate 838 and to the input of inverter 844. When the vertical lines in the leading half of the lower portion of the portrait background move beyond the air gap of magnetic head 210, as they will do approximately 438 milliseconds after switch 156 closed, the 0 at the output of FREQUENCY DETECTOR will be changed back to a 1. Thereupon, the 1 which NOR gate 800 was applying to the clock input of COUNTER 804 will be changed back to a 0.

Approximately 456 milliseconds after switch 156 closed, the vertical grid lines in the trailing half of the upper portion of the portrait background will move into engagement with the air gap of the magnetic head 208. Neither the OVERLEVEL SENSING sub-block 296 nor the BORDER sub-block 516 will change the output thereof in response to the resulting amplified pulses from amplifier 790. However, the FREQUENCY DETECTOR 792 will respond to those amplified pulses, in essentially the same manner in which it responded to the amplified pulses corresponding to the leading half of the upper portion of that portrait background, to again cause NOR GATE 800 to apply a 1 to the clock input of COUNTER 804. Inverter 819 will be responding to the 0 at output terminal 4 of that COUNTER to apply a 1 to the data input terminal of that COUNTER; and hence the 1 at the clock input of that COUNTER will cause the COUNTER to develop a 1 at output terminal 1 thereof. That 1 at that terminal will not be significant because that output terminal is not connected to anything; but the resulting application of 1's to output terminals 2 and 3 of that COUNTER will cause NAND gate 834 to apply a 0 to the upper input of NOR gate 838 and to the input of inverter 844. That NOR gate will continue to apply a 0 to the input of RELAY DRIVER 884 because conductor 242 continues to apply a 1 to the lower input of that NOR gate; but inverter 844 will apply a 1 to the lower input of exclusive OR gate 846. The resulting 1 on conductor 850 is regarded as a VALIDATION signal; but it will not affect the output of NOR gate 290 at this time because conductor 764 is applying a 1 to the upper input of that NOR gate, and it will not affect the output of NAND gate 240 at this time because NAND gate 232 and inverter 238 are applying a 0 to the upper input of NAND gate 240. The resulting 0 on conductor 852 will not affect the output of NOR gate 288 at this time because conductor 768 is applying a 1 to the middle input of that NOR gate; and the resulting 0 at the lower input of NAND gate 268 will not be significant at this time because conductor 260 is applying a 0 to the middle input of that NAND gate.

Approximately 468 milliseconds after switch 156 was closed, and hence while the air gap of magnetic head 208 still is in engagement with the trailing half of the upper portion of the portrait background, BINARY COUNTER 254 will again apply a 1 to conductor 256. However, that 1 will not change the output of NAND gate 272 because conductor 260 continues to apply a 0 to the lower input of that NAND gate.

When the vertical grid lines in the trailing half of the upper portion of the portrait background move beyond the air gap of magnetic head 208, as they will do approximately 472 milliseconds after switch 156 closed, the 0 at the output of FREQUENCY DETECTOR 792 will be changed back to a 1. Thereupon, the 1 which NOR gate 800 was applying to the clock input of COUNTER 804 will be changed back to a 0.

Approximately 497 milliseconds after switch 156 was closed, the vertical grid lines in the trailing half of the lower portion of the portrait background will move into engagement with the air gap of the magnetic head 210. Neither the OVERLEVEL SENSING sub-block 296 nor the porder sub-block 516 will change the output thereof in response to the resulting amplified pulses from amplifier 790. However the FREQUENCY DETECTOR 792 will respond to those amplified pulses, in essentially the same manner in which it responded to the amplified pulses corresponding to the leading half of the upper portion of that portrait background, to again cause NOR gate 800 to apply a 1 to the clock input of COUNTER 804. Inverter 819 will be responding to the 0 at output terminal 4 of that COUNTER to apply a 1 to the data input terminal of that COUNTER; and hence the 1 at the clock input of that COUNTER will cause that COUNTER to develop a 1 at output terminal 1 thereof. That 1 at that output terminal will not be significant because that output terminal is not connected to anything; but the resulting application of 1's to output terminals 2 and 3 of that COUNTER will continue to cause NAND gate 834 to apply a 0 to the upper input of NOR gate 838 and to the input of inverter 844. That NOR gate will continue to apply a 0 to the input of RELAY DRIVER 884 because conductor 242 continues to apply a 1 to the lower input of that NOR gate; and inverter 844 will continue to apply a 1 to the lower input of exclusive OR gate 846. The COUNTER 804 will develop a 1 at output terminal 4 thereof, and inverter 819 will respond to that 1 to apply a 0 to the data input terminal of that COUNTER.

Approximately 532 milliseconds after switch 156 closed, the trailing half of the lower portion of the portrait background will move beyond the air gap of the magnetic head 210; and, at such time, the 0 at the output of FREQUENCY DETECTOR 792 will again be changed back to a 1. Thereupon, the 1 which NOR gate 800 was applying to the clock input of COUNTER 804 will be changed back to a 0.

It will be noted that the leading half of the upper portion of the portrait background of the inserted bill engages and moves beyond the air gap of the magnetic head 208 before the leading half of the lower portion of that portrait background can engage the air gap of the magnetic head 210. That leading half of that lower portion of that portrait background will move beyond the air gap of magnetic head 210 before the trailing half of the upper portion of that portrait background can engage the air gap of the magnetic head 208. That trailing half of that upper portion of that portrait background will move beyond the air gap of magnetic head 208 before the trailing half of the lower portion of that portrait background can engage the air gap of the magnetic head 210. As a result, the magnetic heads 208 and 210 can coact with the four herein-described portions of an inserted bill to provide separate four groups of amplified pulses which are spaced apart in point of time.

Immediately before the trailing half of the lower portion of the portrait background moves beyond the air gap of magnetic head 210, the leading edge of the "0" of the "ONE," which is intermediate that portrait background and the trailing border of the inserted bill, will engage the air gap of magnetic head 208. The resulting pulses from that magnetic head will be amplified by amplifier 790 and applied to the OVERLEVER SENSING sub-block 296, to the BORDER subblock 516, and to the FREQUENCY DETECTORS 792, and 794. The amplitude of the resulting amplified pulses will not be great enough to cause that OVERLEVEL SENSING sub-block to change the 0 at the output thereof to a 1; and the frequency of those amplified pulses will be quite different from the frequencies to which those FREQUENCY DETECTORS are set. As a result, those amplified pulses will not affect that OVERLEVEL SENSING sub-block or those FREQUENCY DETECTORS. Those amplified pulses will cause the BORDER sub-block 516 of FIG. 4 to charge the capacitor 712; but the NOR gates 706 and 708 will continue to act as an electronic latch which will maintain a continuous 0 on conductor 517.

Approximately 535 milliseconds after switch 156 closed, BINARY COUNTER will apply a 1 to conductor 260. However, at this time, that 1 will not be able to change the output of NAND gate 268 because 0's are applied to the upper and lower input of that NAND gate, will not be able to change the output of NAND gate 270 because a 0 is being applied to the lower input of that NAND gate, and will not be able to change the output of NAND gate 272 because 0's are applied to the upper and middle inputs of that NAND gate.

The "ONE" between the portrait background and the trailing border of the inserted bill will coact with the magnetic heads 208 and 210 to provide repeated pulses to the amplifier 790 until the E of that "ONE" has moved beyond the air gap of magnetic head 210. However, the resulting amplified pulses from amplifier 790 will be unable to change the output of any of OVERLEVEL SENSING sub-block, of BORDER sub-block 516, and of FREQUENCY DETECTORS 792 and 794.

Approximately 602 milliseconds after switch 156 closed, the BINARY COUNTER 254 will again apply a 1 to conductor 256. However, that 1 will not affect the output of NAND gate 272; because conductor 258 is applying a 0 to the middle input of that NAND gate.

Approximately 700 milliseconds after the leading edge of the inserted bill caused actuator 148 to move far enough to close switch 146, the trailing edge of that bill will permit that actuator to move far enough in the opposite direction to permit that switch to re-open. The resulting 1 at the lower input of NOR gate 758 will cause that "NOR" gate to apply a 0 to conductor 764 and to the input of inverter 770 -- with consequent application of a 1 to conductor 776. The 0 on conductor 764 will not affect the output of NOR gate 290 because conductor 850 is applying a 1 to the lower input of that NOR gate; and that 0 will not affect the output of NOR gate 294 because conductor 768 is applying a 1 to the lower input of that NOR gate. The resulting 1 on conductor 776 will not affect the output of NAND gate 232 because conductors 766 and 780 are applying 0's to the middle and lower inputs of that NAND gate; and that 1 will not affect the output of NOR gate 288 because conductor 768 is applying a 1 to the middle input of that NOR gate. The 1 on conductor 766 will not affect the output of NOR gate 292 because conductor 778 is applying a 1 to the middle input of that NOR gate; but the 1 on conductor 776 will cause the output of NOR gate 518 to change from 1 to 0. The inverter 520 will respond to that 0 to apply a 1 to conductor 522 and thus to the lower input of each of NOR gates 800 and 802 in FIG. 3C -- thereby isolating the outputs of FREQUENCY DETECTORS 792 and 794 from the COUNTERS 804 and 806.

Approximately 668 milliseconds after switch 156 closed, BINARY COUNTER 254 will again apply a 1 to conductor 258. However, that 1 will not affect the outputs of any of NAND gates 266, 268 and 272; because inverter 264 is applying a 0 to the upper input of NAND gate 266, because conductor 852 is applying a 0 to the lower input of NAND gate 268, and conductor 256 is applying a 0 to the upper input of NAND gate 272.

Approximately 680 milliseconds after the leading edge of the inserted bill caused actuator 158 to move far enough to close switch 156, the trailing edge of that bill permitted that actuator to move far enough in the opposite direction to permit that switch to re-open. The resulting 0 on conductor 778 will not affect the output of NOR gate 292 because conductor 776 is applying a 1 to the upper input of that NOR gate. The 0 on conductor 778 will back bias the diode 346 in the OVERLEVEL SENSING sub-block 296 of FIG. 7, and thereby keep 0 on conductor 297 which is connected to the output of that sub-block. The 0 on conductor 778 will cause NAND gate 698 in BORDER sub-block 516 in FIG. 4 to change 0 at the output thereof to a 1; and it will thereby disable the electronic "latch" constituted by that NAND gate and NAND gate 696, and also will disable the electronic "latch" constituted by NOR gates 706 and 708. At this time, NAND gate 698 will have a 1 at its lower input and a 0 at its upper input. NAND gate 700 will have a 0 at the lower input thereof and a 1 at the upper input therof; and NAND gate 696 will have 1's at both inputs thereof. Also, NOR gate 706 will have 0's at both inputs thereof, while NOR gate 708 will have 1's at both inputs thereof.

The 1 on conductor 766 will not change the output of NAND gate 232 because conductor 780 is applying a 0 to the lower input of that NAND gate. That 1 will change the output of NAND gate 246 to a 0; and NAND gate 248 will respond to that 0 to apply a 1 to the reset terminal of BINARY COUNTER 254 -- thereby re-setting all of the output terminals of that BINARY COUNTER to 0. The 1 on conductor 766 will not change the output of NOR gate 294 because conductor 768 is applying a 1 to the lower input of that NOR gate.

Approximately 700 milliseconds after the leading edge of the inserted bill caused actuator 164 to move far enough to close switch 162, the trailing edge of that bill will permit that actuator to move far enough in the opposite direction to permit that switch to re-open. The resulting 1 at the lower input of NOR gate 760 will cause that NOR gate to apply a 0 to conductor 768 and to the input of inverter 774 -- with resultant application of a 1 to conductor 780. The 0 on conductor 768 will not change the output of NOR gate 288 because conductor 776 is applying a 1 to the upper input of that NOR gate; and that 0 will not change the output of NOR gate 294 because conductor 766 is applying a 1 to the middle input of that NOR gate.

The resulting 1 on conductor 780 will be applied to the lower input of NAND gate 232 and will change the output of that NAND gate from a 1 to a 0, because conductors 776 and 766 are applying 1's to the upper and middle inputs of that NAND gate. The resulting 0 on conductor 234 will be applied to the lower input of NAND gate 328, but the output of that NAND gate will not change because NAND gate 326 is applying a 0 to the upper input of that NAND gate. However, the 0 at the input of inverter 238 will cause that inverter to apply a 1 to the upper input of NAND gate 240 and to the cathode of diode 245. That NAND gate will change the 1 on conductor 242 to a 0; and the resulting 0 at the upper input of NAND gate 246 will cause that NAND gate to apply a 1 to the lower input of NAND gate 248. The latter NAND gate will change the 1 at the output thereof, and hence at the reset input terminal of BINARY COUNTER 254, to a 0 -- thereby permitting that BINARY COUNTER to again start counting the pulses from PULSE GENERATOR 252. The 0 which conductor 242 applies to the lower input of NAND gate 251 will not change the output of that NAND gate because the forward biasing of diode 245 had been maintaining a 0 at the upper input of that NAND gate. The 0 which conductor 242 applies to the input of inverter 264 will cause that inverter to apply a 1 to the upper input of NAND gate 266; but the output of that NAND gate will not change because conductor 258 is applying a 0 to the lower input of that NAND gate, the 0 which conductor 242 applies to the input of inverter 762 in FIG. 3B will cause that inverter to apply a 1 to the upper inputs of NOR gates 758 and 760; but the outputs of those NOR gates will remain 0 because 1's are applied to the lower inputs of those NOR gates. However, the 1's which are applied to the upper inputs of NOR gates 758 and 760 will keep any further closings of switches 146 and 162 from changing the outputs of those NOR gates.

The 0 which conductor 242 applies to the lower input of NOR gate 840 in FIG. 3C will not change the output of that NOR gate, because NAND gate 836 is applying a 1 to the upper input of that NOR gate. However, the 0 which conductor 242 applies to the lower input of NOR gate 838 will cause that NOR gate to apply a 1 to the input of RELAY DRIVER 884; and, thereupon, the relay coil 888 will respond to the 0 at the output of that RELAY DRIVER to become energized. At this time, the dispensing machine can start the dispensing of the desired change.

The 1 which inverter 238 applied to the cathode of diode 245 will back bias that diode; and thus will permit the source of regulated plus 12 volts D.C. to apply a 1 to the upper input of NAND gate 251. However, because of the 0 which conductor 242 is now applying to the lower input of that NAND gate, a 1 will continue to appear at the output of that NAND gate.

The 1 which conductor 780 applies to the lower input of NAND gate 270 will not be significant at this time because conductor 260 is applying a 0 to the upper input of that NAND gate. The 1 which conductor 780 applies to the middle input of NOR gate 290 will not be significant at this time because conductor 850 is applying a 1 to the lower input of that NOR gate. The 1 which conductor 780 applies to the lower input of NOR gate 292 will not be significant at this time because conductor 776 is applying a 1 to the upper input of that NOR gate. The 1 which conductor 780 applies to the lowermost input of NOR gate 518 will not be significant at this time because conductor 776 is applying a 1 to the second lowermost input of that NOR gate.

Approximately 67 milliseconds after switch 162 reopened, the BINARY COUNTER 254 will again apply a 1 to conductor 256; but that 1 will not be effective at this time because NAND gate 272 has 0's at the middle and lower inputs thereof. Approximately 134 milliseconds after switch 162 reopened, BINARY COUNTER 254 will apply a 1 to conductor 258; but that 1 will not change the output of NAND gate 268 because 0's appear at the middle and lower inputs of that NAND gate, and that 1 will not change the output of NAND gate 272 because conductors 256 and 260 will cause 0's to appear at the upper and lower inputs of that NAND gate. However, the application of that 1 to the lower input of NAND gate 266 will coact with the 1 at the upper input of that NAND gate to cause that NAND gate to apply a 0 to conductor 278, and hence to the second uppermost inputs of NAND gates 728 and 730 in FIG. 3B. The resulting 1's on -- -- conductors 734 and 736 will appear at the reset inputs of COUNTERS 804 and 806. Because COUNTER 806 did not receive any clock pulses from NOR gate 802 as the one dollar bill passed through the bill transport, that COUNTER will already be in its reset state. However, the 1 on conductor 736 will reset COUNTER 804; and hence 0 will appear at all of the outputs thereof and thus at the input of inverter 819 and at both inputs of NAND gate 834. The resulting 1 at the output of that NAND gate will be applied to the upper input of NOR gate 838 and to the input of inverter 844. The resulting 0 at the input of RELAY DRIVER 884 will cause that RELAY DRIVER to apply a 1 to the left-hand end of relay coil 888, thereby de-energizing that relay coil. The 1 at the input of inverter 844 will cause that inverter to apply a 0 to the lower input of EXCLUSIVE OR gate 846; and that EXCLUSIVE OR gate will change the 1 on conductor 850 back to 0 and will apply a 1 to the input of inverter 848. That inverter will respond to that 1 to change the 0 on conductor 852 back to a 1.

The 0 which conductor 850 will apply to the lower input of NOR gate 290 will not affect the output of that NOR gate, because conductor 780 is applying a 1 to the middle input of that NOR gate. However, the 0 which is applied to the lower input of NAND gate 240 will cause that NAND gate to change the 0 on conductor 242 back to a 1. The 1 which that conductor will apply to the upper input of NAND gate 246 will coact with the 1 at the lower input of that NAND gate to cause that NAND gate to apply a 0 to the lower input of NAND gate 248. The resulting 1 at the output of the latter NAND gate will reset BINARY COUNTER 254, and will thereby cause that BINARY COUNTER to apply 0's to all of conductors 256, 258 and 260; and that BINARY COUNTER will remain in its reset condition as long as NAND gate 248 applies a 1 to the reset input terminal thereof. Conductor 258 will apply a 0 to the lower input of NAND gate 266, and the resulting 1 at the output of that NAND gate will apply a 1 to conductor 278 and to the second uppermost inputs of NAND gates 728 and 730. Those NAND gates will then apply 0's to conductors 734 and 736, and thus to the reset input terminals of COUNTERS 804 and 806. The 1 which conductor 242 applies to the lower input of NAND gate 251 will coact with the 1 at the upper input of that NAND gate to cause that NAND gate to apply a 0 to the interconnected inputs of NAND gate 434 of the SPEED MAINTAINING sub-block 358 of FIG. 6. The resulting 1 at the base of transistor 438 will render that transistor conductive, and hence diode 444 will be forwarded biased to apply a 0 to the upper inputs of NAND gates 448 and 450. The resulting 1 at the output of the latter NAND gate will forward bias transistor 466; and the consequent 0 at the base of transistor 468 will render the latter transistor non-conductive. Thereupon, transistor 480 and then transistor 482 will become non-conductive, and the motor 562 will become de-energized. However, the continued energization of that motor, for 134 milliseconds after switch 162 reopened, made certain that the inserted bill was moved wholly beyond the trailing edges of the platens 40 and 118 of the bill transport.

The 1 which conductor 242 applies to the input of inverter 264 will cause that inverter to apply a 0 to the upper input of NAND gate 266; but that 0 will not change the output of that NAND gate because 0 is being applied to the lower input of that NAND gate. The 1 which conductor 242 applies to the input of inverter 762 in FIG. 3B will cause that inverter to apply 0's to the upper inputs of NOR gates 758 and 760. However, those 0's will not affect the outputs of those NOR gates because 1's are being applied to the lower inputs of those NOR gates. The 1 on conductor 242 will be applied to the lower inputs of NOR gates 838 and 840; but that 1 will not change the outputs of those NOR gates because 1's are being applied to the upper inputs of those NOR gates.

The 1 on conductor 852 will be applied to the lower input terminal of NAND gate 268; but that 1 will not change the output of that NAND gate because conductors 258 and 260 are applying 0's to the upper and middle inputs of that NAND gate. The 1 on conductor 852 also will be applied to the lower input of NOR gate 288, but that 1 will not change the output of that NOR gate because conductor 776 is applying a 1 to the upper input of that NOR gate.

At this time, the paper currency validator will have completed one cycle of operation, and it will again be in its at-rest condition. During that cycle of operation, that paper currency validator responded to an authentic U.S. 1 dollar bill to energize the relay coil 888 in the dispensing machine for 134 milliseconds, and it also moved that bill into the bill-receiving area, not shown, of that dispensing machine. Preferably, that area will include a bill stacker of the type disclosed and claimed in Gustav F. Erickson application Ser. No. 375,417 for Escrow-Stacker For Paper Currency which was filed Aug. 3, 1973.

For the purposes of this detailed description of the operation of the paper currency validator, it was assumed that an authentic U.S. 1 dollar bill had been introduced into the bill transport 30 of FIG. 1. If that bill had been an authentic U.S. 5 dollar bill, the operation of the paper currency validator would have been identical, except that the FREQUENCY DETECTOR 792 would not have responded to the amplified pulses from amplifer 790; and hence COUNTER 804 would have remained inactive, and relay coil 888 would not have been energized. Instead, FREQUENCY DETECTOR 794 would have responded to the amplified pulses from the amplifier 790 to repeatedly change the 1 at the output thereof to 0, and thereby cause NOR gate 802 to apply a succession of 1's to the clock input of COUNTER 806. NAND gate 836 would have responded to the resulting 1's at output terminals 2 and 3 of that COUNTER to apply a 0 to the upper input of NOR gate 840 and to the input of inverter 842. The 0 at the upper input of that NOR gate would have cooperated with the 0 which conductor 242 was applying to the lower input of that NOR gate to cause that NOR gate to apply a 1 to RELAY DRIVER 886 - thereby causing that RELAY DRIVER to energize the relay coil 890 in the dispensing machine. Inverter 842 would have responded to the 0 at the input thereof to cause EXCLUSIVE OR gate 846 to apply a 1 to conductor 850 and, via inverter 848, a 0 to conductor 852. As a result it can be seen that the insertion of an authentic U.S. 5 dollar bill into the bill transport 30, in the same manner in which the authentic U.S. 1 dollar bill was inserted into that bill transport, would cause the paper currency validator to experience a cycle of operation during which it would energize the relay coil 890 for 134 milliseconds and would move the inserted bill to the bill-receiving area of the dispensing machine. Thereafter, that paper currency validator would again assume its at-rest condition.

If, instead of disposing an authentic U.S. one dollar bill so the bottom of the portrait of George Washington was close to the flange 142 on the cover 140, a patron were to insert such a bill so the top of that portrait was close to that flange, the border which had been the trailing border in the prior detailed description of the paper currency validator would now be the leading border of that bill. As a result, the "ONE" which is intermediate that border and the portrait background will engage the air gaps of the magnetic heads 208 and 210 before the portrait background can engage those air gaps. The magnetic ink in the "ONE" will cause the magnetic heads 208 and 210 and amplifier 790 to develop amplified pulses that will cause transistor 682 in the BORDER sub-block 516 of FIG. 4 to alternatively become conductive and non-conductive. The resulting succession of 0's and 1's at the upper input of NAND gate 700 will cause that NAND gate to alternately forward bias and back bias diode 702; and hence capacitor 712 will remain charged throughout the time the "ONE" is in engagement with either of the air gaps of magnetic heads 208 and 210. That time can be as long as 130 milliseconds if the air gaps of both of those magnetic heads engage the projections at the free ends of the E of the "ONE," but that time will be shorter if either of those air gaps fails to do so. However, in any event, that time will be longer than 65 milliseconds; and hence the portrait background will engage the air gap of the magnetic head 208 while the capacitor 712 is maintaining a 1 at the interconnected inputs of NOR gate 704 in that BORDER sub-block. Consequently, the diode 713 will be forward biased, and it will maintain a 0 at the upper input of NOR gate 706. That 0 will coact with the 0 at the lower input of that NOR gate to cause that NOR gate to continue to apply a 1 to the conductor 517, and thus to the second uppermost input of NOR gate 518. The latter NOR gate will respond to that 1 to continue to apply a 0 to the input of inverter 520; and that inverter will continue to apply a 1 to the lower inputs of NOR gates 800 and 802 via conductor 522. Those NOR gates will apply continuous 0's to the clock inputs of the COUNTERS 804 and 806, and thus will effectively isolate the FREQUENCY DETECTORS 792 and 794 from the COUNTERS 804 and 806. This means that even though the four quadrants of the portrait background on the bill will cause the magnetic heads 208 and 210 and amplifier 790 to develop amplified pulses, and even though those amplified pulses will cause the FREQUENCY DETECTOR 792 to apply four 0's to the upper input of NOR gate 890, that NOR gate will be unable to apply 1's to the clock input of COUNTER 804. As a result, that COUNTER will continue to apply 0 to the upper and lower inputs of NAND gate 834, and that NAND gate will continue to apply a 1 to the upper input of NOR gate 838 and to the input of inverter 844. The consequent continued 0 at the input of RELAY DRIVER 884 will cause that RELAY DRIVER to prevent energization of the relay coil 888 in the dispensing machine; and the consequent 0 at the lower input of EXCLUSIVE OR gate 846 will cause that EXCLUSIVE OR gate to continue to maintain a 0 on conductor 850 and to cause inverter 848 to continue to maintain a 1 on conductor 852.

The NAND gate 268 in the TIMER LOGIC block 262 will respond to the 1on conductor 852 and to the 1's which will appear at the upper and middle inputs of that NAND gate, approximately 668 milliseconds after switch 156 closed, to change the output thereof from a 1 to a 0. The resulting 0 at the uppermost input of NAND gate 326 will develop a 1 at the output of that NAND gate, and thus at the upper input of NAND gate 328 and also at the input of RELAY DRIVER 330. The resulting 0 at the output of that RELAY DRIVER will be applied by conductor 332 to relay coil 490 in the MOTOR AND RELAY sub-block 360 of FIG. 8 -- causing energization of that relay coil. Thereupon, the movable relay contacts 492 and 494 will be shifted from the "forward" positions shown in FIG. 8 to their right-hand "reverse" positions; and, very promptly, the motor 562 will cause the lower "runs" of belt 198 and of its counterpart to reverse direction and to start moving the bill back toward the front of the bill transport 30.

The 1 which NAND gate 326 applies to the upper input of NAND gate 328 will coact with the 1 which conductor 234 is applying to the lower input of that NAND gate to cause that NAND gate to apply a 0 to conductor 334 - and hence to the second lowermost inputs of NAND gates 728 and 730. The resulting 1's on conductors 734 and 736 will be applied to the reset input terminals of COUNTERS 804 and 806 - thereby precluding energization of either of the relay coils 888 and 890.

The 0 at the output of NAND gate 328 will also be applied to the lower input of NAND gate 326; and hence the latter NAND gate will continue to supply a 1 to the upper input of NAND gate 328 even after the 0 at the output of NAND gate 268 changes back to a 1. As a result, NAND gates 326 and 328 will act as an electronic "latch" that will apply a continuous 1 to the input of RELAY DRIVER 330 and that will apply a continuous 0 to the second lowermost inputs of NAND gates 728 and 730. That electronic "latch" will continue to apply that continuous 1 and that continuous 0 until the power to the paper currency validator is interrupted or until all of the switches 146, 156 and 162 have been permitted to reopen and thereby cause NAND gate 232 to re-apply a 0 to conductor 234.

The motor 562 will continue to drive the lower "runs" of the belt 198 and of its counterpart in the "reverse" direction until the bill 212 successively moves beyond the actuator 164 of switch 162 to permit that switch to reopen, beyond the actuator 158 of switch 156 to permit that switch to reopen, and beyond the actuator 148 of switch 146 to permit that switch to reopen. As the switch 156 reopens, the conductor 766 will again supply a 1 to the lower input of NAND gate 246; and that 1 will coact with the 1 which conductor 242 is applying to the upper input of that NAND gate to cause that NAND gate to apply a 0 to the lower input of NAND gate 248. The resulting 1 at the reset input terminal of BINARY COUNTER 254 will cause 0's to appear on conductors 256, 258 and 260. The 1 which conductor 766 applies to the middle input of NOR gate 294 will not be significant at this time because conductor 764 will be applying a 1 to the upper input of that NOR gate; and the 1 which conductor 766 applies to the middle input of NAND gate 232 will not be significant at this time because conductor 776 will be applying a 0 to the upper input of that NAND gate. The 0 which conductor 778 applies to the OVERLEVEL SENSING block 296 will not be significant at this time, and the 0 which that conductor applies to the middle input of NOR gate 292 will not be significant at this time, but the 0 which that conductor applies to the BORDER sub-block 516 will keep capacitor 712 charged -- and thus will keep a 1 on conductor 517.

As the switch 146 reopens, conductor 764 will apply 0's to the upper inputs of NOR gates 290 and 294, but the outputs of those NOR gates will be unchanged. Also, the conductor 776 will apply a 1 to the upper inputs of NOR gates 288 and 292 and to the second lowermost input of NOR gate 518, but the outputs of those NOR gates will remain unchanged. However, NAND gate 232 will respond to the 1 on conductor 776 to apply a 0 to the lower input of NAND gate 328 and to the input of inverter 238. NAND gate 328 will apply a 1 to the lowermost input of NAND gate 326 and, via conductor 334, will apply a 1 to the second lowermost inputs of NAND gates 728 and 730. Thereupon, those NAND gates will apply 0's to conductors 734 and 736 and thus to the re-set inputs of COUNTERS 804 and 806. The inverter 238 will apply a 1 to the upper input of NAND gate 240, and that NAND gate will continue to apply a 1 to conductor 242. The 1 which inverter 238 applies to the cathode of diode 245 will back bias that diode, and the source of regulated plus twelve volts D.C. will start charging the capacitor 249. After a few milliseconds, that capacitor will have charged to a value at which a 1 will appear at the upper input of NAND gate 251; and that 1 will coact with the 1 which conductor 242 is applying to the lower input of that NAND gate to cause that NAND gate to apply a 0 to the interconnected inputs of NAND gate 434 in the SPEED MAINTAINING sub-block 358 of FIG. 6. The resulting 1 at the output of that NAND gate will render transistor 438 conductive, and will thereby forward bias diode 444 to apply a 0 to the upper inputs of NAND gates 448 and 450. The resulting 1 at the base of transistor 466 will cause transistors 468, 480 and 482 to become non-conductive -- thereby causing the motor 562 to come to rest.

All of this means that the presence of a number of magnetic ink lines intermediate the leading border and the portrait background of a bill will reverse the motor 562 and will prevent energization of either of the relay coils 888 and 890. Consequently, the inserted bill will be returned to the patron who inserted it, and the dispensing machine will be kept from dispensing change. In the preferred embodiment of the present invention, instructions are suitably affixed to the upper surface of the platform to urge patrons to dispose bills with the black-ink face up and with the bottom of the portrait close to the flange 142 on the cover 140.

If an authentic U. S. 5 dollar bill were to be inserted in the bill transport 30 so the "FIVE," which is located between the leading border and the portrait, would engage the air gaps of the magnetic heads 206 and 208 before the portrait background could engage those air gaps, the motor 562 would reverse and the relay coils 888 and 890 would remain un-energized. Specifically, the magnetic heads 208 and 210 and amplifier 790 would respond to the "FIVE" on the five dollar bill to develop amplified pulses which would cause the "BORDER" sub-block 516 of FIG. 4 to keep capacitor 712 charged until the F of the "FIVe" moved beyond the air gap of the magnetic head 210. At such time, the portrait background would be so close to the air gap of the magnetic head 208 that there would not be enough time to permit capacitor 712 to discharge and for capacitor 716 to charge before that portrait background engaged that magnetic head. The resulting continued 1 on conductor 517 would cause NOR gate 518 and inverter 520 to apply a 1 to NOR gates 800 and 802; and those NOR gates would effectively isolate the FREQUENCY DETECTORS 792 and 794 from the COUNTERS 804 and 806. As a result, the NAND gate 836 would apply a 1 to the upper input of NOR gate 840 and to theinput of inverter 842; and hence relay coil 890 would remain un-energized, and conductor 852 would apply a 1 to the lower input of NAND gate 268. Approximately 668 milliseconds after switch 156 was closed, conductors 258 and 260 would apply 1's to the upper and middle inputs of NAND gate 268; and, thereupon, that NAND gate would change the output thereof from 1 to 0, and NAND gate 326 would respond to the resulting 0 at the upper input thereof to cause RELAY DRIVER 330 and the MOTOR AND RELAY sub-block 360 to reverse the motor 562. The overall result is that the five dollar bill would be moved back out of the bill transport 30, and the relay coils 888 and 890 in the dispensing machine would remain un-energized.

As indicated by the two immediately preceding explanations of the operation of the currency validator by bills which have the "ONE" or "FIVE" thereof disposed ahead of the portrait background, whenever a 0 is applied to any of the inputs of NAND gate 326, the RELAY DRIVER sub-block 330 and the MOTOR AND RELAY sub-block 360 will reverse the motor 562. Also, the NAND gate 328 will cause NAND gates 728 and 730 to reset the COUNTERS 804 and 806; and the re-setting of those COUNTERS will make certain that relay coils 888 and 890 remain un-energized. All of this means that if a 0 is applied to any of the inputs of NAND gate 326, the inserted bill will be returned to the patron who inserted it and the dispensing machine will not dispense change.

In an alternate embodiment of the paper currency validator provided by the present invention, a capacitor 892 is connected between ground and the junction of resistor 684 and the base of transistor 682 in the BORDER sub-block 516, all as shown by FIG. 11. That capacitor acts as an integrator; and it reduces the amplitudes of the amplified pulses which conductor 791 apply to the base of that transistor. The reduction in the amplitude of the amplified pulses which correspond to the "ONE," that is located between the portrait and the leading border of an authentic U.S. 1 dollar bill, will keep those amplified pulses from rendering conductive the transistor 682 in the BORDER sub-block 516. In permitting transistor 862 to remain non-conductive, that capacitor enables that alternate form of the paper currency validator to accept authentic U.S. 1 dollar bills whether the bottom or the top of the portrait of George Washington is close to the flange 142 on the cover 140. Consequently, that capacitor permits "two way insertion" of one dollar bills.

Similarly, the capacitor 892 will reduce the amplitudes of the amplified pulses which correspond to the "FIVE" that is located between the portrait and the leading border of an authentic U.S. 5 dollar bill, and thus will keep those amplified pulses from rendering conductive the transistor 682 in the BORDER sub-block 516. In permitting transistor 862 to remain non-conductive, that capacitor enables that alternate form of the paper currency validator to accept authentic U.S. 5 dollar bills whether the bottom or the top of the portrait of Abraham Lincoln is close to the flange 142 on the cover 140. Consequently, that capacitor permits "two way insertion."

If a person were to attempt to make a spurious one dollar bill, by using a copying machine which utilizes metallic particles in producing images, by using magnetic ink to print a simulation of a bill, or by using magnetic ink to draw a simulation of a bill, that spurious bill would be rejected; because the particles on that simulated bill would have magnetic properties that were far more intense than are the magnetic properties of the black ink on an authentic U.S. bill. Specifically, as the leading edge of the leading border on that simulated bill engaged the air gap of the magnetic head 208, that magnetic head would generate pulses which, when amplified by amplifier 790, would render the transistor 338 in the OVERLEVEL SENSING sub-block 296 of FIG. 7 conductive. The resulting voltage drop across resistor 342 would forward bias transistor 346, and thereby render that transistor conductive. The resulting 1 at the collector of that transistor would be applied by conductors 297 and 284 to the upper input of NOR gate 295; and the resulting 0 at the output of that NOR gate would be applied to the cathode of diode 320. The consequent forward biasing of that diode would cause a 0 to appear at the second lowermost input of NAND gate 326 -- with resulting reversal of motor 562 and with resulting re-setting of COUNTERS 804 and 806, all as pointed out hereinbefore. This means that the instant the magnetic head 208 engages lines which contain substantially more magnetic properties than do the lines in an authentic U.S. dollar bill, the OVERLEVEL SENSING sub-block 296 will effect reversal of the motor 562 and will prevent any and all dispensing of change.

Similarly, if a person were to attempt to make a spurious 5 dollar bill, by using a copying machine which utilizes metallic particles in producing images, by using magnetic ink to print a simulation of a bill, or by using magnetic ink to draw a simulation of a bill, that spurious bill would be rejected; because the particles on that simulated bill would have magnetic properties that were far more intense than are the magnetic properties of the black ink on an authentic U.S. bill. Specifically, as the leading edge of the leading border on that simulated bill engaged the air gap of the magnetic head 208, the OVERLEVEL SENSING sub-block 296 would effect reversal of the motor 562 and would prevent any and all dispensing of change.

If a person who made such a simulation of a bill was able to learn that the intensity of the magnetic material in the leading border of the bill was causing rejection of that simulated bill, that person might try to decrease the intensity of the magnetic material in that leading border by use of an eraser, by use of water, by use of soap, or by use of some other material - removing material. Even if that person were able to reduce the intensity of the magnetic material in that leading border to a value which enabled the corresponding amplified pulses to be below the threshold level of transistor 338 in OVERLEVEL SENSING sub-block 296 and yet be above the threshold levels of transistor 682 in FIG. 11 and of the phase locked loops in FREQUENCY DETECTORS 792 and 794, the paper currency validator of the present invention would still reject that simulated bill. Specifically, the magnetic material in the succeeding lines on the simulated bill would cause the magnetic head 208 to generate pulses which, when amplified by the amplifier 790, would render conductive the transistor 338 in the OVERLEVEL SENSING sub-block 296 -- with consequent reversal of the motor and with consequent resetting of the COUNTERS 804 and 806. That reversal and that re-setting would occur whether those succeeding lines were the vertical grid lines in the portrait background, were the lines in the "ONE" or "FIVE," or any other lines on the simulated bill.

Even if a person who used magnetic material to make a simulation of a bill was able to reduce the intensity of all of that material to a value which enables the corresponding amplified pulses to be below the threshold level of transistor 338 in OVERLEVEL SENSING sub-block 296 and yet be above the threshold levels of transistor 682 in FIG. 11 and of the phase locked loops in FREQUENCY DETECTORS 792 and 794, the paper currency validator of the present invention would reject that simulated bill if a "ONE" or "FIVE" of that simulated bill engaged the air gaps of the magnetic heads 208 and 210 before the portrait background on that simulated bill engaged those air gaps. Specifically, at the time the "ONE" or the "FIVE" on that simulated bill engaged the air gap of the magnetic head 208, ewither the capacitor 712 in the BORDER sub-block 516 would still have a charge large enough to enable it to apply a 1 to the interconnected inputs of NOR gate 704, or the capacitor 716 would have little or no charge and thus would be applying a 0 to the upper input of NOR gate 706. In either event, conductor 517 would be applying a 1 to the second uppermost input of NOR gate 518, and inverter 520 would be applying a 1 to the lower inputs of NOR gates 800 and 802 -- thereby keeping the COUNTERS 804 and 806 from receiving pulses from the FREQUENCY DETECTORS 792 and 794. The resulting continued 1's at the upper inputs of NOR gates 838 and 840 would keep the relay coils 888 ands 890 in the dispensing machine un-energized; and the resulting continued 1's at the inputs of inverters 842 and 844 would cause EXCLUSIVE OR gate 846 to continue to maintain a 1 on conductor 852 -- with consequent reversal of the motor 562 approximately 668 milliseconds after switch 156 closed. In this way, the BORDER sub-block 516 will effect the rejection of a simulated bill if that simulated bill has magnetic ink lines spaced across the area intermediate the leading border and the portrait -- even if the intensity of all of the magnetic material on that simulated bill is comparable to that of the material in the magnetic ink used to engrave authentic U.S. bills, and regardless of the source of or reason for those magnetic ink lines.

If a person could insert an authentic U.S. bill in the bill transport 30 and somehow keep the leading edge of that bill from moving the actuator 164 far enough to close the switch 162, the paper currency validator would reverse the motor 562 and would keep the relay coils 888 and 890 un-energized. In such event, the operation of that paper currency validator could, from the time the switch 146 was closed until approximately 300 milliseconds after the switch 156 was closed, be identical to the normal initial operation of that paper currency validator. However, approximately 300 milliseconds after the switch 156 was closed, the conductor 780 would not apply a 0 to the lower input of NAND gate 270 and, instead, would continue to apply a 1 to that lower input. Moreover, that conductor would continue to apply that 1 to that lower input until approximately 535 milliseconds after switch 156 was closed. At that time, the BINARY COUNTER 254 would apply a 1 to conductor 260, and thus to the upper input of NAND gate 270, and that NAND gate would apply a 0 to the second uppermost input of NAND gate 326. Thereupon, as explained hereinbefore, the motor 562 would start operating in the reverse direction and COUNTERS 804 and 806 would be re-set.

If a person could insert an authentic U.S. bill in the bill transport 30 and somehow keep the trailing edge of that bill from freeing the actuator 158 of the switch 156, the paper currency validator would reverse the motor 562 and would keep the relay coils 888 and 890 de-energized. In such event, the operation of that paper currency validator could, from the time the switch 146 was closed until approximately 680 milliseconds after the switch 156 was closed, be identical to the normal initial and intermediate operation of that paper currency validator. At such time, the switch 156 should be open; because an authentic bill is 6 1/8 inches long, and it should have moved the trailing edge thereof at least half an inch beyond the actuator 158 of that switch. However, if that switch was still closed, approximately 680 milliseconds after that switch was closed, the conductor 766 would not apply a 1 to the lower input of NAND gate 246. Instead, that conductor would continue to apply a 0 to that lower input, and hence NAND gate 246 would cause NAND gate 248 to continue to apply a 0 to the reset input terminal of BINARY COUNTER 254 -- thereby permitting that BINARY COUNTER to continue counting the pulses from the PULSE GENERATOR 252. Approximately 735 milliseconds after switch 156 was closed, that BINARY COUNTER would apply 1's to conductors 256, 258 and 260, and thus to all of the inputs of NAND gate 272. The resulting 0 at the output of that NAND gate would cause inverter 274 to forward bias diode 276 -- with consequent application, via conductor 284, of a 1 to the uppermost input of NOR gate 295. The 0 which that NOR gate would apply to the cathode of diode 320 would forward bias that diode, and thereby cause a 0 to appear at the second lowermost input of NAND gate 322 -- with consequent reversal of motor 562 and with consequent resetting of COUNTERS 804 and 806.

If a person inserted an authentic U.S. bill with the green-ink face thereof up, if a person inserted a Xerox copy of the black-ink face of an authentic U.S. bill, or if a person inserted any other object which did not have magnetic ink on the upper face thereof, the paper currency validator would reverse the motor 562 and would keep the relay coils 888 and 890 un-energized. In such event, the operation of that paper currency validator could, from the time the switch 146 was closed until approximately 140 milliseconds after the switch 156 was closed, be identical to the normal initial operation of that paper currency validator. However, approximately 140 milliseconds after the switch 156 was closed, the magnetic head 708 and the amplifier 790 would not supply amplified pulses to the base of transistor 682 in the BORDER sub-block 516; and hence that BORDER sub-block would continue, via conductor 517, to apply a 1 to the second uppermost input of NOR gate 518. The resulting 0 at the output of that NOR gate would cause inverter 520, via conductor 522, to apply 1's to the lower inputs of NOR gates 800 and 802, thereby effectively isolating the clock input terminals of COUNTERS 804 and 806 from the outputs of the FREQUENCY DETECTORS 792 and 794. Subsequently, when the leading and trailing edges of the upper portion of the portrait background engaged the air gap of the magnetic head 208, that magnetic head would not develop any pulses. Similarly, when the leading and trailing edges of the lower portion of that portrait background engaged the air gap of the magnetic head 210, that magnetic head would not develop any pulses. This means that neither of the FREQUENCY DETECTORS 792 and 794 would apply a 0 to the upper input of the adjacent NOR gate. For these various reasons, the COUNTERS 804 and 806 would continue to apply 0's to all of the output terminals thereof; and NAND gates 834 and 836 would coact with NOR gates 838 and 840 and with RELAY DRIVERS 884 and 886 to keep the relay coils 888 and 890 un-energized. Also, those NAND gates would coact with inverters 844 and 842 and with EXCLUSIVE OR gate 846 to continue to maintain a 0 on conductor 850, and thus at the lower input of NOR gate 290, and to continue to maintain a 1 on conductor 852, and thus at the lower input of NAND gate 268. This means that when switch 146 re-opened -- approximately 700 milliseconds after that switch was closed conductor 764 would be applying a 0 to the upper input of NOR gate 290, conductor 780 would be applying a 0 to the middle input of that NOR gate, and conductor 850 would be applying a 0 to the lower input of that NOR gate. Thereupon, that NOR gate would apply a 1 to the anode of diode 300; and the resulting forward biasing of that diode would cause conductor 284 to apply a 1 to the upper input of NOR gate 295. The 0 which the latter NOR gate would apply to the cathode of diode 320 would forward bias that diode and permit a 0 to appear at the second lowermost input of NAND gate 326 -- with consequent reversal of the motor 572, all as explained hereinbefore.

If the re-opening of switch 146 happened to occur more than 668 milliseconds after the switch 156 was closed, the BINARY COUNTER 254 would, via conductors 258 and 260, apply 1's to the upper and middle inputs of NAND gate 268. Those 1's would coact with the 1 which conductor 852 would be applying to the lower output of that NAND gate to cause that NAND gate to apply a 0 to conductor 780, and thus to the upper input of NAND gate 326. Thereupon, the latter NAND gate would cause the motor 562 to reverse, all as explained hereinbefore.

If a person were to insert a long object into the bill transport 30 and close the switch 162, the paper currency validator would start the motor 562 operating in the reverse direction and would keep the relay coils 888 and 890 unenergized. Specifically, as that switch was closed, conductor 780 would apply a 0 to the middle input of NOR gate 290; and that 0 would coact with the 0 which conductor 764 would be applying to the upper input of that NOR gate and with the 0 which conductor 850 would be applying to the lower input of that NOR gate to cause that NOR gate to apply a 1 to the anode of diode 300. The resulting forward biasing of that diode would cause conductor 284 to apply a 1 to the upper input of NOR gate 295; and the 0 which that NOR gate would apply to the cathode of diode 320 would forward bias that diode and permit a 0 to appear at the second lowermost input of NAND gate 326 -- with consequent re-setting of the COUNTERS 804 and 806 with consequent shifting of the relay contacts 492 and 494 in the MOTOR AND RELAY sub-block 360 of FIG. 8 to their "reverse" positions. This means that when the motor 562 started, as it would when switch 162 was closed, that motor would start operating in the reverse direction.

If a person were to insert a U.S. authentic bill in the bill transport 30, and then immediately thereafter insert a further U.S. authentic bill in that bill transport, the paper currency validator would reject both of those bills. Specifically, if the first bill was holding switch 162 closed, but had moved far enough inwardly of the bill transport 30 to permit switch 156 to re-open, the closing of switch 146 by the leading edge of the second bill would cause conductor 776 to apply a 0 to the upper input of NOR gate 292. At that time, conductor 778 would be applying a 0 to the middle input of that NOR gate, and conductor 780 would be applying a 0 to the lower input of that NOR gate; and hence that NOR gate would apply a 1 to the middle input of NOR gate 295. The resulting 0 at the output of the latter NOR gate would forward bias diode 320 and thereby cause a 0 to appear at the second lowermost input of NAND gate 326. Thereupon, that NAND gate would reverse the motor 562 and also would re-set the COUNTERS 804 and 806, all as explained hereinbefore.

In making certain that two authentic U.S. bills which were inserted in the bill transport 30 in rapid succession would be rejected, the switches 146, 156 and 162 and the NOR gate 292 also make certain that the motor 562 would reverse and that the COUNTERS 804 and 806 would be re-set in the event a tape, a ribbon, or other "tail," that would move actuator 148 but not actuator 158, was attached to an authentic U.S. bill. Specifically, as the belt 198 and its counterpart moved such a bill inwardly of the bill transport 30, that bill would successively close switches 146, 156 and 162; and that "tail" would continue to hold switch 146 closed as the trailing edge of the bill moved beyond the actuator 158 and permitted switch 156 to re-open. At such time, the conductors 776, 778 and 780 would be applying 0's to the upper, middle, and lower inputs of NOR gate 292; and that NOR gate would be applying a 1 to the middle input of NOR gate 295. The resulting 0 at the output of the latter NOR gate would forward bias diode 320 and thereby cause a 0 to appear at the second lowermost input of NAND gate 326 -- with consequent reversal of motor 562 and with consequent re-setting of COUNTERS 804 and 806.

If a person were to insert just a short portion of the length of an authentic U.S. bill, or were to insert any object that had a configuration which would cause it to hold switch 156 closed at a time when switches 146 and 162 were open, the paper currency validator would reverse the motor 562 and would reset the COUNTERS 804 and 806. Specifically, such a portion of a bill or such an object would permit switch 146 to apply a 0 to the upper input of NOR gate 294 via NOR gate 758 and conductor 764, switch 156 would apply a 0 to the middle input of NOR gate 294 via conductor 766, and switch 162 would apply a 0 to the lower input of that NOR gate via NOR gate 760 and conductor 768. Consequently, NOR gate 294 would apply a 1 to the lower input of NOR gate 295; and the latter NOR gate would apply a 0 to the cathode of diode 320. The resulting forward biasing of that diode would apply a 0 to the second lowermost input of NAND gate 326; and thus would effect reversal of the motor 562 and the re-setting of COUNTERS 804 and 806, all as described hereinbefore.

Various configurations of an object could cause that object to permit switches 146 and 162 to be open when switch 158 was closed. For example, a short object of almost any configuration could keep switch 158 closed while permitting switches 146 and 162 to be open, a long object with notches in the leading and trailing edges thereof could permit switches 146 and 162 to be open while the switch 156 was closed, and a long object with an opening in register with the actuator 148 of switch 146 could close switch 156 while switches 146 and 162 were open. However, regardless of the configuration of the object which was inserted in the bill transport 30, if that object closed switch 156 when switches 146 and 162 were open, the paper currency validator would reverse the motor 562 and would re-set the COUNTERS 804 and 806.

The NOR gate 294 and the switch 156 will effect the reversal of motor 562 and the re-setting of COUNTERS 804 and 806 in the event an authentic U.S. bill is equipped with a tape, ribbon or other "tail" that will engage the actuator 158 of that switch but will not engage either of the actuators of switches 146 and 162. Specifically, as such a tail-equipped bill passed inwardly through the bill transport 30, that bill would successively close switches 146, 156 and 162, would pass beyond the actuator 148 to permit the switch 146 to re-open, would pass beyond the actuator 158, and would pass beyond the actuator 164 to permit the switch 162 to re-open. However, the "tail" would not permit the actuator 158 to move far enough to permit the switch 156 to re-open; and at such time, conductors 764, 766 and 768 would be applying 0's to the upper, middle and lower inputs of NOR gate 294. The resulting 1 at the lower input of NOR gate 295 would cause that NOR gate to forward bias diode 320, and would thereby cause a 0 to appear at the second lowermost input of NAND gate 326. At such time, the motor 562 would reverse and the COUNTERS 804 and 806 would be re-set, all as explained hereinbefore.

If a person made or obtained a simultated bill which was similar, or even identical to an authentic U.S. bill in all respects other than the spacing between the leading edges of the vertical grid lines in the portrait background, the paper currency validator of the present invention would reject that simulated bill. The bill transport 30 would respond to the invertion of that simulated bill to start the motor 562; and, until the leading half of the upper portion of the portrait background of that simulated bill engaged the air gap of the magnetic head 208, the operation of the paper currency validator would be the same as the normal operation of that paper currency validator. However, the signals which the leading and trailing halves of the upper portion of the portrait background on the simulated bill would cause the magnetic head 208 to develop, and the signals which the leading and trailing halves of the lower portion of that portrait background would cause the magnetic head 210 to develop, would not have the frequencies to which the phase locked loops of the FREQUENCY DETECTORS 792 and 794 will respond; and hence the COUNTERS 804 and 806 would not receive 1's at the clock input terminals thereof. As a result, those COUNTERS would leave the relay coils 888 and 890 un-energized, and also would leave the 0 on conductor 850 and the 1 on conductor 852. This means that when switch 146 re-opened -- approximately seven hundred milliseconds after that switch was closed -- conductor 764 would be applying a 0 to the upper input of NOR gate 290, conductor 780 would be applying a 0 to the middle input of that NOR gate, and conductor 850 would be applying a 0 to the lower input of that NOR gate. Thereupon, that NOR gate would apply a 1 to the anode of diode 300; and the resulting forward biasing of that diode would cause conductor 284 to apply a 1 to the upper input of NOR gate 295. The 0 which the latter NOR gate would apply to the cathode of diode 320 would forward bias that diode and permit a 0 to appear at the second lowermost input of NAND gate 326 -- with consequent reversal of the motor 572, all as explained hereinbefore.

If the re-opening of switch 146 happened to occur more than 668 milliseconds after the switch 156 was closed, the BINARY COUNTERS 254 would, via conductors 258 and 260, apply 1's to the upper and middle inputs of NAND gate 268. Those 1's would coact with the 1 which conductor 852 would be applying to the lower output of that NAND gate to cause that NAND gate to apply a 0 to conductor 780, and thus to the upper input of NAND gate 326. Thereupon, the latter NAND gate would cause the motor 562 to reverse, all as explained hereinbefore.

To provide a high rejection rate for simulated bills, it is necessary that the bandpasses of the phase locked loops in the FREQUENCY DETECTORS 792 and 794 be narrow and fixed; and, as indicated herein, the widths of those bandpasses are only plus and minus five percent. Also, it is necessary that the speed of the motor 562 be maintained within narrow, fixed limits; and the SPEED ADJUSTING sub-block 356 of FIG. 5 maintains that speed within such limits.

That SPEED ADJUSTING sub-block is identical to the similarly-numbered SPEED ADJUSTING sub-block in Thaddeus M. Jones application for SPEED CONTROLLING SYSTEM which is being filed of even date and which bears Docket No. 18154 of Rogers, Ezell and Eilers. The A.C. generator 560 in the MOTOR AND RELAY sub-block 360 of FIG. 8 will supply signals to the full-wave bridge rectifier 376 in the SPEED ADJUSTING sub-block 356 via conductors 368 and 370; and those signals will have the form of a periodic wave form that has an integral number of periods for each revolution of the shaft of the motor 562. The full-wave bridge rectifier 376 will rectify those signals and will apply rectified pulses to the base of transistor 378; and that transistor will act as a high gain amplifier and will respond to those rectified pulses to be driven hard into saturation. Consequently, that transistor will develop steep-sided flat-bottomed negative going pulses at the collector thereof; and, because rectifier 376 is a full-wave rectifier, the frequency of those negative-going pulses will be double the frequency of the signals supplied by conductors 368 and 370.

The diode 389 will by-pass to the source of regulated plus twelve volts any positive-going output from the transistor 378; and the capacitor 386 and the resistor 390 will differentiate the negative-going pulses from that transistor. The resulting differentiated pulses will be applied to pin 2 of the MONOSTABLE MULTIVIBRATOR 392; and that MONOSTABLE MULTIVIBRATOR will respond to those differentiated pulses to provide output pulses at pin 3 thereof. Those output pulses will have the same frequency as the differentiated pulses which are applied to pin 2, but each of those output pulses will have the same precisely fixed duration. The MONOSTABLE MULTIVIBRATOR 392 is set so the durations of those output pulses will always keep the duty cycle of those pulses less than one hundred percent -- even when the motor 562 is operating at its maximum speed. In this way, that MONOSTABLE MULTIVIBRATOR causes the transistor 414 to respond to the frequency of the output pulses at pin 3 rather than to any harmonics of that frequency.

The resistor 412 applies the output pulses at pin 3 of the MONOSTABLE MULTIVIBRATOR 392 to the base of transistor 414, and it acts to limit the base-emitter current of that transistor to a safe value. That transistor operates as a saturated switch; and, in the preferred embodiment of the present invention, that transistor has an exceedingly low saturation voltage. Resistors 400 and 402 constitute a voltage divider which is connected between ground and the source of regulated twelve volts; and transistor 414 will selectively permit that voltage divider to apply the voltage at the junction between those resistors to the non-inverting input of the operational amplifier 420. Specifically, whenever that transistor is non-conductive, the voltage at the junction between resistors 400 and 402 will tend to be applied to that non-inverting input; but whenever that transistor is conductive ground voltage will tend to appear at that non-inverting input. Resistor 416 and capacitor 418 tend to provide an averaging action; and that averaging will substantially average the changing voltages at the collector of transistor 414 to apply a voltage to the non-inverting input of operational amplifier 420 which is proportional to the duty cycle of the output pulses at pin 3 of MONOSTABLE MULTIVIBRATOR 392, and thus is proportional to the frequency of the pulses which the signals from the A.C. generator 560 cause the full-wave bridge rectifier 376 and the transistor 378 to apply to pin 2 of that MONOSTABLE MULTIVIBRATOR. The transistor 414 and the resistors 400 and 402 constitute one side of a bridge circuit; and the other side of that bridge circuit is constituted by resistors 404 and 406 and potentiometer 408. That bridge circuit is connected between ground and the source of regulated 12 volts, and hence the voltage at any given point in either side of that bridge circuit will vary with variations in the 12 volts. However, any voltage variations at a given point in one side of that bridge circuit, which are due to variations in the 12 volts, should equal the voltage variations, at the corresponding point in the other side of that bridge circuit, which are due to variations in the 12 volts. As a result, although the voltage at the junction between resistors 400 and 402 will vary with variations in the voltage of the source, and although the voltage at the middle contact of the potentiometer 408 also will vary with variations in the voltage of the source, the variations in those voltages which are due to variations in the voltage of the source should be substantially the same. Consequently, the difference between the voltage at the junction between resistors 400 and 402 and the voltage at the movable contact of potentiometer 408 should be essentially independent of and unaffected by variations in the 12 volts; and the operational amplifier 420 responds to the difference.

Specifically, the movable contact of potentiometer 408 is connected to the inverting input of operational amplifier 420, and, as pointed out hereinbefore, resistor 416 and capacitor 418 tend to provide an averaging acting of the changing voltage at the collector of transistor 414 and apply the resulting average voltage to the non-inverting input of that operational amplifier. That operational amplifier is connected as a summing integrator, and hence it can respond to a difference between the voltages applied to the inputs thereof to develop an output voltage; and thereafter it can maintain that output voltage constant even though both input voltages become the same. That operational amplifier enables the SPEED ADJUSTING sub-block 356 to control the speed of the motor 562 with an exceedingly high degree of accuracy. Thus, in the said one preferred embodiment, that operational amplifier enables that SPEED ADJUSTING sub-block to limit variations in the speed of the motor 562 to plus or minus 1/4 of 1 percent.

The Zener diode 430 responds to the voltage at the output of the operational amplifier 420 to apply a corresponding, but lesser, voltage to the base of transistor 468; and resistor 432 will limit the current which that operational amplifier can apply to the base-emitter circuit of that transistor. Transistor 468 and transistors 480 and 482 amplify the signal provided by the Zener diode 430, and the transistor 482 can supply sufficient power to drive the motor 562.

The speed of the motor 562 is set by appropriately setting the movable contact of the potentiometer 408; and, in the said preferred embodiment of the present invention, the speed of that motor is set to cause each inserted bill to move at the rate of ten inches per second. The A.C. generator 560 will respond to rotation of the shaft of the motor 562 to supply sine waves to the SPEED ADJUSTING sub-block 356; and that sub-block will respond to the frequency, rather than to the amplitude, of the sine waves which are developed by the A.C. generator 560. As a result, that sub-block minimizes the effects which variations in the temperature of the motor and which variations in the 12 volts could have on the speed of motor 562. In actual practice, it has been found that the signals which the SPEED ADJUSTING sub-block 356 applies to the base of transistor 468 are effectively independent of even substantial changes in the temperature of the motor, whereas the output signals of speed adjusting circuits which respond to the amplitude of sine waves developed by a tachometer can vary as much as plus or minus 16 percent.

The SPEED ADJUSTING sub-block 356 is not, per se, a part of the present invention; and, for a more detailed explanation of the manner in which it controls the speed of the motor 562, reference should be made to the said Jones application. However, the inclusion of the SPEED ADJUSTING sub-block 356 in the overall circuit of the paper currency validator of the present invention is very desirable because that SPEED ADJUSTING sub-block and the phase locked loops in the FREQUENCY DETECTORS 792 and 794 make it commercially practical to set the pass bands of plus and minus five percent for those phase locked loops. The SPEED ADJUSTING sub-block 356 controls the speed of the motor 562 so closely that, insofar as the speed of inserted bills was concerned, it would be possible to make the passbands for the phase locked loops even narrower. However, the inherent variations in the engravings on authentic U.S. bills coact with the dimensional changes in those bills due to moisture and to wear and folding to require band passes of plus or minus 5 percent.

The current which drives the motor 562 flows from the source of regulated 24 volts via the collector-emitter circuit of transistor 482, conductor 366, relay contacts 492, motor 562, relay contacts 494, conductor 372, and then either through resistor 502 to ground or through resistors 504 and 506 to ground. The voltage at the junction between resistors 504 and 506 is applied to the base of transistor 500 by a resistor 508; but, under normal conditions of operation of the motor 562, the voltage at the base of that transistor will be so close to ground that the transistor 500 will remain non-conductive. However, in the event the value of the current flowing through the motor 562 were to increase appreciably, the voltage at the junction between resistors 504 and 506 would increase to the point where transistor 500 was forward biased; and, thereupon, that transistor would become conductive. The resulting 0 at the input of inverter 512 would cause that inverter to apply a 1 to conductor 374, and thus to the upper input of NOR gate 518 in the COUNT ENABLE block 514, of FIG. 3B. The resulting 0 at the output of that NOR gate would cause inverter 520 to apply a 1 to conductor 522, and hence to the lower inputs of NOR gates 800 and 802 in FIG. 3C. The resulting 0's at the clock inputs of the COUNTERS 804 and 806 would keep those COUNTERS from applying 1's to the input of NAND gates 834 and 836.

The current flowing through the motor 562 would increase to a value which would render conductive the transistor 500, in the CURRENT SENSING sub-block 362, of FIG. 8, only in the event a person inserted a bill or other object in the bill transport 30 and then retarded or halted inward movement of that bill or object. As the inward movement of that bill or object was retarded or halted, the frequency of the signal which the A.C. generator 560 applied to the MONOSTABLE MULTIVIBRATOR 392 via conductors 368 and 370, full-wave bridge rectifier 376, resistor 380, transistor 378 and capacitor 386 would decrease; and the SPEED ADJUSTING sub-block 356 of FIG. 5 would respond to that decrease in frequency to sharply increase the voltage at the output of operational amplifier 420. The resulting increase in the current flowing through motor 562 and resistor 506 would cause the voltage at the junction between that resistor and resistor 504 to increase to the point where transistor 500 becomes conductive.

If the person halted further inward movement of the bill before the leading edge of that bill closed the switch 162, and if that person held that bill stationary for 535 milliseconds after the switch 156 was closed, NAND gate 270 would respond to the 1 which conductor 260 would apply to the upper input thereof and to the 1 which the conductor 780 would apply to the lower input thereof to apply a 0 to the second uppermost input of NAND gate 326 -- thereby causing the motor 562 to reverse and causing re-setting of the COUNTERS 804 and 806 in the manner described hereinbefore. If that person halted the inward movement of the bill after the leading edge of that bill had closed switch 162 but before the appropriate COUNTER 804 and 806 had acted through the adjacent NAND gate and inverter to cause the EXCLUSIVE OR gate 846 and the inverter 848 to change the 1 on conductor 852 to a 0, and if that person held that bill or object stationary until approximately 668 milliseconds after the switch 156 was closed, NAND gate 268 would respond to the 1's which conductors 258, 260 and 852 would be applying to the upper, middle and lower inputs thereof to apply a 0 to the uppermost input of NAND gate 326. At such time, the latter NAND gate would effect reversal of the motor 562 and re-setting of the COUNTERS in the manner explained hereinbefore. If a person did not halt the inward movement of the inserted bill or object but did retard that inward movement sufficiently to cause the CURRENT sensing sub-block 362 to apply a 1 to conductor 374, the continued 0 on conductor 850 would, at the time switch 146 re-opened, coact with the 0's at the upper and middle inputs of NOR gate 290 to cause that NOR gate to forward bias diode 300. At such time, NOR gate 295, diode 320 and NAND gate 326 would cause the motor 562 to reverse and would cause the COUNTERS 804 and 806 to re-set, all as explained hereinbefore. If, a person halted or retarded the inward movement of the inserted bill or object and thereby caused that bill or object to keep switch 156 closed approximately 735 milliseconds after that switch was closed, NAND gate 272 and inverter 274 would coact with diode 276, NOR gate 295, diode 320 and NAND gate 326 to cause the motor 562 to reverse and to cause the COUNTERS 804 and 806 to re-set.

If a person were to halt or were to appreciably retard the inward movement of an authentic U.S. bill after one of the COUNTERS 804 and 806 had caused the adjacent NAND gate and inverter to apply a 0 to the upper input of the adjacent NOR gate and to the input of the adjacent inverter, and if that halting or retarding was merely momentary in nature, the belt 198 and its counterpart would move that bill into the billreceiving area of the dispensing machine. The subsequent reopening of switches 162 would enable NAND gate 232 and inverter 238 to re-apply a 1 to the upper input of NAND gate 240; and that 1 would coact with the 1 which conductor 850 would be applying to the lower input of that NAND gate to enable that NAND gate to apply 0's to the lower input of NOR gates 838 and 840 -- with consequent energization of the appropriate relay coil 888 or 890. This means that if a person retarded or halted the inward movement of an authentic U.S. bill after the VALIDATING AND VENDING LOGIC block 784 had applied a 1 to conductor 850 and a 0 to conductor 852, that person could effect energization of the appropriate relay coil 888 or 890 by promptly releasing that bill. However, if such a person retarded or halted the inward movement of such a bill long enough to cause that bill to keep switch 156 closed approximately 735 milliseconds after that switch was closed, NAND gate 272 and inverter 274 would coact with diode 276, NOR gate 295, diode 320 and NAND gate 326 to cause the motor 562 to reverse and to cause the COUNTERS 804 and 806 to re-set -- all as explained hereinbefore. In these various ways, the paper currency validator fully protects both the persons and the owner of the dispensing machine.

In the event a person halted the inward movement of an authentic U.S. bill after the VALIDATING AND VENDING LOGIC block 784 had applied a 1 to conductor 850 and had applied a 0 to conductor 852, and while that bill was holding switch 162 closed, and if that person thereafter pulled that bill far enough toward the platform 32 to release the actuator 164 of that switch, the paper current validator would reverse the motor 562 and would re-set the COUNTERS 804 and 806. Specifically, as the switch 162 re-opened, conductor 776 would be applying a 0 to the upper input of NOR gate 288, conductor 768 would apply a 0 to the middle input of that NOR gate, and conductor 852 would be applying a 0 to the lower input of that NOR gate. The resulting 1 at the output of that NOR gate would forward bias diode 298 and, thereby would cause conductor 284 to apply a 0 to the upper input of NOR gate 295. The resulting 0 at the cathode of diode 320 would forward bias that diode and thereby apply a 0 to the second lowermost input of NAND gate 326 with consequent reversal of the motor 562 and with consequent re-setting of the COUNTERS 804 and 806 in the manner described hereinbefore.

In the event a person were to mount a portrait of an authentic U.S. bill on a sheet of paper, or were to apply to a sheet of paper a magnetic ink simulation of the portrait background on an authentic U.S. bill, and if that person were to attempt to insert either of those sheets of paper in the bill transport 30, the paper currency validator would reverse the motor 562 and would re-set the COUNTERS 804 and 806. Specifically, because that sheet of paper would not have the leading border which is present on an authentic U.S. bill, the magnetic heads 208 and 210 would not be able to generate pulses as the leading edge of that sheet of paper engaged and passed beneath them. As a result, when the portrait background or the simulation thereof engaged the air gap of the magnetic head 208, the BORDER sub-block 516 would be applying a 1 to the second uppermost input of NOR gate 518. The resulting 0 at the input of inverter 520 would be causing that inverter to apply a 1 to the lower inputs of NOR gates 800 and 802, and would thereby cause 0's to appear at the clock inputs of the COUNTERS 804 and 806.

If the leading half of the upper portion of the portrait background on the sheet of paper caused the magnetic head 208 to develop pulses, the amplifier 790 would apply amplified pulses to the FREQUENCY DETECTORS 792 and 794 and to the BORDER sub-block 516; and the electronic "latch" which is constituted by NAND gates 696 and 698 in that sub-block would respond to those amplified pulses to apply a continuous 1 to the lower input of NAND gate 700 and a continuous 0 to the lower input of NOR gate 708. The transistor 682 in that sub-block would respond to those amplified pulses to recurrently become conductive and nonconductive. The resulting 0's and 1's at the upper input of NAND gate 700 would cause that NAND gate to alternately back bias and forward bias the diode 702; and hence, during the 14 milliseconds while the leading half of the upper portion of the portrait background was in engagement with the air gap of the magnetic head 208, the capacitor 712 would remain charged. During the 32 milliseconds which would elapse after the leading half of the upper portion of the portrait background moved beyond the air gap of the magnetic head 208, and before the leading half of the lower portion of that portrait background engaged the air gap of the magnetic head 210, the capacitor 712 would be discharging through resistor 710. However, at the end of that 32 millisecond period, the charge on that capacitor would still be great enough to maintain a 1 at the interconnected inputs FIVE"NOR gate 704; and hence the BORDER sub-block 516, NOR gate 518, inverter 520, and NOR gates 800 and 802 would still be applying 0's to the clock inputs of COUNTERS 804 and 806. As a result, even if FREQUENCY DETECTOR 792 or FREQUENCY DETECTOR 794 had responded to the amplified pulses from the amplifier 790 to apply a 0 to the upper input of the adjacent NOR gate, that NOR gate would continue to apply a 0 to the clock input of the adjacent COUNTER. This means that neither COUNTER will register a count in response to the engagement between the leading half of the upper portion of the portrait background and the air gap of magnetic head 208. the input

As the leading half of the lower portion of the portrait background subsequently moved into engagement with the air gap of magnetic head 210, that magnetic head and amplifier 790 would apply further amplified pulses to the FREQUENCY DETECTORS 792 and 794 and to the transistor 682 in the BORDER sub-block 516. That transistor, NAND gate 700, and diode 702 would respond to those amplified pulses to recurrently apply charging pulses to the capacitor 712 during the 32 milliseconds while the leading half of the lower portion of the portrait background is in engagement with the air gap of magnetic head 210. As a result, during the time the leading half of the lower portion of the portrait was in engagement with the air gap of the magnetic head 210, the BORDER sub-block 516, NOR gate 518, inverter 520, and NOR gates 800 and 802 would effectively keep any 0 which either of the FREQUENCY DETECTORS 792 and 794 developed at its output from causing the adjacent COUNTER to register a count. During the 18 millisecond interval between the instant the leading half of the lower portion of the portrait background moved beyond the air gap of magnetic head 210 and the instant the trailing half of the upper portion of that portrait background moved into engagement with the air gap of magnetic head 208, the capacitor 712 would be discharging through resistor 710. However, at the end of that eighteen millisecond period, the charge on that capacitor would still be great enough to apply a 1 to the interconnected inputs of NOR gate 704

At the end of the 18 millisecond interval, the trailing half of the upper portion of the portrait background would cause magnetic head 208 and amplifier 790 to apply further pulses to the FREQUENCY DETECTORS 792 and 794 and to the transistor 682 of the BORDER sub-block 516. That transistor, NAND gate 700 and diode 702 would respond to those amplified pulses to supply further charging pulses to capacitor 712, and hence, at the end of the 16 millisecond period of time during which the trailing half of the upper portion of the portrait background was in engagement with the air gap of the magnetic head 208, the capacitor 712 would be applying a 1 to the interconnected inputs of NOR gate 704. During the ensuing 25 millisecond period between the instant the trailing half of the upper portion of the portrait background moved beyond the air gap of magnetic head 208 and the instant the trailing half of the lower portion of that portrait background moved into engagement with the air gap of magnetic head 210, the capacitor 712 would be discharging through resistor 710. However, at the end of that 25 milliseconds, the charge on that capacitor would still be great enough to continue to apply a 1 to the interconnected inputs of NOR gate 704; and hence the BORDER sub-block 516 would continue to apply a 1 to conductor 517, and thus to the second-uppermost input of NOR gate 518. As a result, inverter 520 would continue to apply 1's to the lower inputs of NOR gates 800 and 802, and those NOR gates would effectively keep any 0 which could develop at the output of either of the FREQUENCY DETECTORS 792 and 794 from causing the adjacent COUNTER to register a count.

During the ensuing 35 milliseconds when the trailing half of the lower portion of the portrait background was in engagement with the air gap of the magnetic head 210, that magnetic head and amplifier 790 applied further amplified pulses to the input of the FREQUENCY DETECTORS 792 and 794 and also to the transistor 862 in the BORDER sub-block 516. The capacitor 712 would be re-charged during those 35 milliseconds, and hence the NOR gates 800 and 802 would continue to effectively isolate the FREQUENCY DETECTORS 792 and 794 from the adjacent COUNTER.

All of this means that because the sheet of paper did not have a border which was comparable to the border on an authentic U.S. bill, any 0 which was developed at the output of either of the FREQUENCY DETECTORS 792 and 794 could not have caused the adjacent COUNTER to register a count. Further, it means that neither of the NAND gates 834 and 836 was able to apply a 0 to the upper input of the adjacent NOR gate or to the input of the adjacent inverter. As a result, either when the switch 146 subsequently reopened as the trailing edge of the inserted bill moved inwardly beyond the actuator 148, or approximately 668 milliseconds after the switch 156 was closed, whichever occurs first, the motor 562 would reverse. Specifically, as the switch 146 reopened, NOR gate 290 would have 0's applied to all of the inputs thereof, and the resulting 1 at the output thereof would forward bias diode 300 and thereby cause conductor 284 to apply a 1 to the upper input of NOR gate 295. The resulting 0 at the output of that NOR gate would forward bias the diode 320 and apply a 0 to the second lowermost input of NAND gate 326, with consequent reversal of the motor 562 and with consequent re-setting of the COUNTERS 804 and 806. If the switch 146 did not re-open before approximately 668 milliseconds after switch 156 was closed, NAND gate 268 would have 1's applied to all of the inputs thereof, and it would apply a 0 to the uppermost input of NAND gate 326, with consequent reversal of the motor 562 and with consequent re-setting of the COUNTERS 804 and 806. It thus should be clear that the insertion of a sheet of paper which has the portrait background of an authentic U.S. bill thereon but which does not have a border corresponding to the leading border of such a bill would cause the paper currency validator to reverse the motor 562 and to re-set the COUNTERS 804 and 806.

If a person were to insert into the bill transport 30 an authentic U.S. bill which had been altered so the intensity of the magnetic ink in the leading border thereof was too low, the amplified pulses which magnetic head 208 and amplifier 790 would apply to the BORDER sub-block 516 would not attain the threshold value of transistor 862 in that sub-block. As a result, that transistor would remain non-conductive; and that sub-block would coact with NOR gate 518, inverter 520, and NOR gates 800 and 802 to effectively isolate the COUNTERS 804 and 806 from the FREQUENCY DETECTORS 792 and 794, all as explained hereinbefore. Consequently, the paper currency validator would reject such a bill in the same manner in which it rejected the sheet of paper which had the portrait background of an authentic bill applied to it.

In the event a person were to insert into the bill transport 30 an authentic U.S. bill which had a denomination other than a one or a five, the pulses which the magnetic heads 208 and 210 would generate as the appropriate portions of the portrait background moved past the air gaps of those magnetic heads would frequencies to which the phase locked loop, in the FREQUENCY DETECTORS 792 and 794 could not respond. As a result, the insertion of any such U.S. bills would leave 0's at the outputs of the COUNTERS 804 and 806, and hence the NAND gates 834 and 836 would continue to apply 1's to the upper inputs of NOR gates 838 and 840 and to the inputs of inverters 842 and 844. Consequently, the motor 562 would reverse approximately 668 milliseconds after switch 156 was closed or when inward movement of the inserted bill permitted the switch 146 to reopen, whichever occurred first. In this way, the paper currency validator of the present invention protects a patron against the loss of a high denomination bill through the inadvertent insertion of that bill in the bill transport 30.

If a person were to obtain or make an object which had a leading border that closely simulated the leading border of an authentic U.S. bill, and which had parallel lines of magnetic material on the upper face thereof that were spaced so they caused each of the FREQUENCY DETECTORS 792 and 794 to apply four clock pulses to its COUNTER as that bill or object moved past the magnetic heads 208 and 210, those COUNTERS would cause the NAND gates 834 and 836 to apply 0's to the upper inputs of NOR gates 838 and 840 and to the inputs of inverters 844 and 842. The resulting 1 at both inputs of the EXCLUSIVE OR gate 846 would cause that EXCLUSIVE OR gate to continue to apply a 0 to conductor 850 and to the input of inverter 848. The resulting 1 on conductor 852, and the resulting 0 on conductor 850, would cause the motor 562 to reverse and would cause the COUNTERS 804 and 806 to re-set approximately 668 milliseconds after the switch 156 was closed or as the trailing edge of the inwardly moving bill permitted the switch 146 to re-open, whichever occurred first. This means that any object which could cause both COUNTERS 804 and 806 to receive cour counts as that object moved past the magnetic heads 208 and 210 would be rejected.

In the event any of the switches 146, 156 or 162 were to be held closed, either deliberately or accidentally, for more than seventeen seconds, the RC network which is constituted by resistor 460 and capacitor 458 in the SPEED MAINTAINING sub-block 358 of FIG. 6 would be "time out." As the switch 146 closes during each operation of the paper currency validator, NAND gate 251 will apply a 1 to the conductor 253, and thus to the inter-connected inputs of NAND gate 434 in FIG. 6. The resulting 0 at the output of the latter NAND gate will make transistor 438 non-conductive, and the consequent 1 at the collector of that transistor will back bias the diode 444. NAND gate 448 will respond to the 1 at the upper input thereof and to the 1 at the lower input thereof to apply a 0 to the anode of diode 456; and the resulting back biasing of that diode will permit the capacitor 450 to start discharging through the resistor 460. However, in the normal operation of the paper currency validator, the inserted bill will move inwardly and will successively permit the switches 146, 156 and 162 to re-open in less than one second, or the motor 562 will reverse and that bill will move back out of the bill transport 30, and thereby permit all of those switches to re-open, in less than 2 seconds. Consequently, during the normal operation of the paper currency validator, the switches 146, 156 and 162 will re-open, and will cause NAND gate 232, inverter 238, diode 245 and NAND gate 251 to re-apply a 0 to the interconnected inputs of NAND gate 434 -- with consequent re-charging of capacitor 458 -- long before the charge on that capacitor can decrease to a level at which the 1 which that capacitor applies to the lower input of NAND gate 450 could become a 0. However, if any of the switches 146, 156 and 162 are held closed for more than seventeen seconds, the capacitor 458 would be permitted to discharge for that length of time; and the charge on that capacitor would decrese to the point where the 1 at the lower input of NAND gate 450 would change to a 0. Thereupon, a 1 would be applied to the base of transistor 466; and that transistor would again become conductive and would thereby again render the transistor 468, 480 and 482 non-conductive. At such time, the motor 562 would come to rest.

When that closed switch re-opened, either accidentially or as a result of positive action, the resulting 0 at the output of NAND gate 232 would cause inverter 238 to back bias the diode 245; and the resulting 1 at the upper input of NAND gate 251 would coact with the 1 which conductor 242 was applying to the lower input of that NAND gate to cause that NAND gate to reapply a 0 to the interconnected inputs of NAND gate 434 in FIG. 6. Consequently, the re-opening of that switch would permit the SPEED MAINTAINING sub-block 358 of FIG. 6 to resume its at-rest position.

In the foregoing description of the operation of the paper currency validator by an authentic U.S. 1 dollar bill, it was assumed that the magnetic head 208, the amplifier 790 and the FREQUENCY DETECTOR 792 applied two time-spaced 0's to the upper input of NOR gate 800, and thereby caused that NOR gate to apply two time-spaced 1's to the clock input of COUNTER 804. Also it was assumed that the magnetic head 210 coacted with amplifier 790 and FREQUENCY DETECTOR 792 to apply two further time-space 0's to the upper input of NOR gate 800, and thereby caused that NOR gate to apply two further time-space 1's to the clock input of that COUNTER. However, because the pulses which are developed by the oscillator in the phase locked loop in the FREQUENCY DETECTOR 792 may randomly be in or out of phase with the amplified pulses from the FREQUENCY DETECTOR 792, that phase locked loop may in a small percentage of instances respond to the four time-spaced amplified pulses from the amplifier 790 to apply just three time-spaced 0's to the upper input of NOR gate 800 even though an authentic U.S. 1 dollar bill is being sensed. In that small percentage of instances, that NOR gate will be able to supply just three time-spaced 1's to the clock input of the COUNTER 804; but, as long as the movable contacts 808 and 810 are in the lower positions shown by FIG. 4, that COUNTER will be able to respond to those 1's to apply 1's to both inputs of NAND gate 834.

If, at any time, one or more persons were able to cause a simulation of an authentic U.S. bill to make the magnetic heads 208 and 210, the amplifier 790, the FREQUENCY DETECTOR 792, and the NOR gate 800 apply three but not four 1's to the clock input of COUNTER 804, it would be a simple matter to shift the movable contacts 808 and 810 to their upper positions. Thereupon, any such person or persons would be kept from improperly energizing the relay coils 888 and 890. Specifically, when the movable contacts 808 and 810 are shifted into their upper positions, the movable contact 808 will not apply a 1 to the upper input of NAND gate 834 until a 1 appears at the fourth output terminal of the COUNTER 804. Consequently, any simulated bill which could cause the VALIDATING AND VENDING LOGIC block 784 of FIG. 3C to apply three, but not four, time-spaced 1 to the clock input of the COUNTER 804 could not cause that counter to apply a 1 to the input of NAND gate 834. Consequently, the paper currency validator would keep the relay coils 888 and 890 un-energized and would subsequently reverse the motor 562.

In the event the phase locked loop in the FREQUENCY DETECTOR 792 were to respond to amplified pulses from the amplifier 790, which were 100 and 80.degree. out of phase with the pulses generated by the oscillator of that phase locked loop, to cause that FREQUENCY DETECTOR to apply five time-spaced 0's to the upper input of NOR gate 800, even though an authentic U.S. one dollar was being sensed that NOR gate would apply five time-spaced 1's to the clock input of COUNTER 804. If, at the time the fifth 1 was applied to the clock input of the COUNTER 804, the contacts 808 and 810 were in the lower positions shown by FIG. 3C, the 1 at the output terminal 818 would cause inverter 819 to apply a 0 to the data input terminal of that COUNTER. As a result, that fifth 1 would cause a 0 to appear at output terminal one of that COUNTER; but 1's would continue to appear at output terminals three and four of that COUNTER. Consequently, NAND gate 834 would continue to have 1's applied to both inputs thereof, and would continue to apply 0's to the upper input of NOR gate and to the input of inverter 844.

If the movable contacts 808 and 810 had been in their upper positions, the fourth 1 at the clock input of COUNTER 804 would have caused the 0 which inverter 819 was applying to the data input terminal of that COUNTER to appear at output terminal one. Then, as the fifth 1 was applied to that clock input, the 0 on output terminal one would appear at output terminal two and the 0 which inverter 819 was applying to the data input terminal of COUNTER 804 would appear at output terminal one. However, because contact 808 was connected to output terminal four rather than to output terminal two, and because contact 810 was energizing output terminal 828, the NAND gate 834 would continue to have 1's applied to both inputs thereof, and would continue to apply 0's to the upper input of NOR gate and to the input of inverter 844.

All of this means that whether the movable contacts 808 and 810 are in the lower positions shown by FIG. 3C or are in their upper positions, the COUNTER 804 will be able to respond to five 1's at the clock input thereof to apply 1's to both inputs of NAND gate 834. Consequently, if, in responses to amplified pulses that are derived from an authentic U.S. one dollar bill, the phase locked loop of the FREQUENCY DETECTOR 792 produces five rather than four time-spaced 0's, the paper currency validator will accept that bill and will energize the relay coil 888.

However, if, a sixth 1 is applied to the clock input of COUNTER 804, while the contacts 808 and 810 are in their lower positions, the 0 which appeared at output terminal one as a result of the fifth 1 at the clock input would respond to the sixth 1 to appear at output terminal two. The resulting application by contact 808 of a 0 to the upper input of NAND gate 834 will change the 0's at the upper input of NOR gate 838 and at the input of inverter 844 to 1's. If that sixth 1 is applied to the clock input of COUNTER 804, while the contacts 808 and 810 are in their upper positions, the 0 which appeared at output terminal two as a result of the fifth 1 at the clock input would respond to the sixth 1 to appear at output terminal three. The resulting application of a 0 to the lower input of NAND gate 834, by the conductor which extends from the output terminal three to that lower input, will change the 0's at the upper input of NOR gate 838 and at the input of inverter 844 to 1's.

If a seventh 1 is applied to the clock input of COUNTER 804, while the contacts 808 and 810 are in their lower positions, the 0's which appeared at output terminals one and two as a result of the sixth 1 would respond to that seventh 1 to appear at output terminals two and three. The resulting application of 0's to both inputs of NAND gate 834 will change the 0's at the upper input of NOR gate 838 and at the input of inverter 844 to 1's. If that seventh 1 is applied to the clock input of COUNTER 804, while the contacts 808 and 810 are in their upper positions, the 0's which appeared at output terminals two and three as a result of the sixth 1 would respond to the seventh 1 to appear at output terminals three and four. The resulting application of 0's to both inputs of NAND gate 834 will change the 0's at the upper input of nor gate 838 and at the input of inverter 844 to 1's.

All of this means that if an inserted bill or other object causes the VALIDATING AND VENDING LOGIC block 784 to produce a count of two or less or to produce a count of six or more, when the contacts 808 and 810 are in their lower positions, the paper currency validator will not energize either of the relay coils 888 and 890, and that paper currency validator will subsequently reverse the motor 562 and thereby move the inserted bill or object back out of the bill transport 30. Further, it means that if an inserted bill or other object causes the VALIDATING AND VENDING LOGIC block 784 to produce a count of six or more, when the contacts 808 and 810 are in their upper positions, the paper currency validator will energize neither of the relay coils 888 and 890, and that paper currency validator will subsequently reverse the motor 562 and thereby move the inserted bill or object back out of the bill transport 30.

The switches that are constitued by the movable contacts 820 and 822 and the stationary contacts 824, 826, 828 and 830 will coact with the COUNTER 806 to provide comparable acceptance of 5 dollar bills and comparable rejection of 5 dollar bills. Thus, when the contacts 820 and 822 are in their lower positions, authentic U.S. 5 dollar bills will be accepted if the VALIDATING AND VENDING LOGIC block 784 provides three, four or five counts; but relay coil 890 will remain un-energized and motor 562 will reverse if that block provides two or less or six or more counts. When the contacts 820 and 822 are in their upper positions, authentic U.S. 5 dollar bills will be accepted if the VALIDATING AND VENDING LOGIC block 784 provides four or five counts; but relay coil 890 will remain un-energized and motor 562 will reverse if that block provides three or less or six or more counts.

Normally the movable contacts 808, 810, 820 and 822 will be set in their lower positions, because those contacts provide a higher acceptance rate for authentic U.S. bills when they are in those lower positions. However, those contacts will be set in their upper positions if any person or persons is able to cause a simulation of an authetic U.S. bill to make the magnetic heads 208 and 210, the amplifier 790, the FREQUENCY DETECTOR 792 or the FREQUENCY DETECTOR 794 and the adjacent NOR gate apply three but not four 1's to the clock input of the adjacent COUNTER.

In the at-rest condition of the paper currency validator, the dispensing machine with which that paper currency validator is associated will be applying a 1 to terminal 526 and a 1 to terminal 530 of the COUPLING block 524 in FIG. 3B. Diodes 536 and 538 will limit the voltages which can be applied to the opto-couplers 540 and 542, but those voltages will be sufficient to cause the light-emitting diodes of those opto-couplers to cause light to fall upon the light-sensitive elements of those opto-couplers. The resulting 0 at the input of diode 548 will forward bias that diode and thereby apply a 0 to the upper input of NAND gate 720 and to the input of inverter 724. The 0 at the upper input of NAND gate 720 will cause that NAND gate to apply 1 to the input of inverter 722, with consequent application of a 0 to the middle input of NOR gate 758. The 0 at the input of inverter 724 will cause that inverter to apply 1 to the lowermost input of NAND gate 728. The 0 at the output of opto-coupler 542 will forward bias diode 550 and thereby apply a 0 to the lower input of NAND gate 720 and to the input of inverter 726. The 0 at the lower input of NAND gate 720 will not charge the 1 at the output of that NAND gate. The 0 at the input of inverter 726 will cause that inverter to apply 1 to the lowermost input of NAND gate 730.

All of this means that as long as the dispensing machine applies 1's to terminals 526 and 530 of the COUPLING block 524, that block will not cause the INHIBIT LOGIC block 718 to apply inhibiting signals to the middle input of NOR gate 758 or re-setting signals to the re-set terminals of COUNTERS 804 and 806. However, if the dispensing machine becomes unable to supply change or product in response to the insertion of an authentic U.S. 5 dollar bill into the bill transport 30, that dispensing machine will change the 1 at input terminal 530 of the COUPLING block 524 to a 0. Thereupon, the output of the opto-coupler 542 will become a 1, and the resulting backbiasing of diode 550 will cause a 1 to appear at the lower input of NAND gate 720 and at the input of inverter 726. The 1 at the lower input of NAND gate 720 will not change the 1 at the output of that NAND gate, but the 1 at the input of inverter 726 will cause that inverter to apply a 0 to the lowermost input of NAND gate 730. The resulting 1 at the reset terminal of COUNTER 806 will effectively prevent that counter from responding to any signals from the FREQUENCY DETECTOR 794. Consequently, even if an authentic U.S. 5 dollar bill is inserted in the bill transport 30 and causes the FREQUENCY DETECTOR 794 to develop four proper time-spaced signals, the relay coil 890 will remain un-energized and a 0 will continue to appear on conductor 850 and a 1 will continue to appear on conductor 852. Approximatelu 668 milliseconds after switch 156 was closed or as the trailing edge of the inwardly moving bill permits switch 146 to re-open, whichever occurs first, the motor 562 will be reversed.

If the dispensing machine becomes unable to supply change or product in response to the insertion of an authentic U.S. 1 dollar bill, that dispensing machine will change the 1 at the input terminal 526 of the COUPLING block 524 to a 0. Thereupon, the output of opto-coupler 540 will become a 1 and the resulting back biasing of diode 548 will cause a 1 to appear at the upper input of NAND gate 720 and at the input of inverter 724. If, at that time, the dispensing machine is applying a 1 to the terminal 530 of that COUPLING block, the application of the 1 to the upper input of NAND gate 720 will not change the output of that NAND gate, because optocoupler 542 and diode 550 will continue to apply 0 to the lower input of that NAND gate. However, the 1 at the input of inverter 724 will cause that inverter to apply a 0 to the lowermost input of NAND gate 728, with consequent re-setting of COUNTER 804. Consequently, even if an authentic U.S. 1 dollar bill is inserted in the bill transport 30 and causes the FREQUENCY DETECTOR 792 to apply four proper time-spaced signals to that COUNTER, the relay coil 888 will remain un-energized and a 0 will continue to appear on conductor 850 and a 1 will continue to appear on conductor 852. Approximately 660 milliseconds after switch 156 was closed or as the trailing edge of the inwardly moving bill permits switch 146 to re-open, whichever occurs first, the motor 562 will reverse.

If the dispensing machine is unable to dispense change or product in response to the insertion of an authentic U.S. 5 dollar bill and also is unable to dispense change or product in response to the insertion of an authentic U.S. 1 dollar bill, that dispensing machine will change the 1's at the input terminals 526 and 530 of the COUPLING block 524 to 0's. The resulting 1's at the output of optical-couplers 540 and 542 will back bias the diodes 548 and 550, and will thereby cause 1's to appear at both inputs of NAND gate 720 and at the input of each of the inverters 724 and 726. The resulting 0 at the output of NAND gate 720 will cause inverter 722 to apply a 1 to the middle input of NOR gate 758; and thereafter that NOR gate will apply a continuous 0 to conductor 764 and will cause the inverter 770 to apply a continuous 1 to conductor 776. This means that even if a bill or other object is inserted in the bill transport 30 and closes the switch 146, the motor 562 will remain de-energized. Consequently, that bill transport will be wholly unable to accept and validate any U.S. 1 dollar or 5 dollar bills. The 1's at the inputs of inverters 724 and 726 will cause those inverters to apply 0's to the lowermost inputs of NAND gates 728 and 730; and those NAND gates will apply 1's to the re-set terminals of COUNTERS 804 and 806. In this way the COUPLING block makes certain that the relay coils 888 and 890 will remain un-energized.

The opto-couplers 540 and 542 are useful in isolating the voltages in the paper currency validator from the voltages in the dispensing machine. As a result, that dispensing machine could be connected to the standard and usual 117 volt A.C. sockets which generally are provided in buildings, and yet the paper currency validator can be powered by relatively low-voltage direct current. Further, those opto-couplers avoid the cost, bulk, noise and electromagnetic readiation which the use of electromagnetic relays, that could be used in lieu of those opto-couplers would entail.

Persons have been known to insert an authentic U.S. bill in a paper currency validator and then manipulate the plug at the end of the electric cord of that paper currency validator in the hope that such manipulation could cause the dispensing machine, associated with that paper currency validator, to dispense change or a product. Specifically, such persons have been known to remove that plug from the socket therefor and then repeatedly and rapidly reinstate and remove that plug, thereby applying a succession of electrical impulses to the circuit of the paper currency validator. Such a practice, which is known as "line cording" could not cause the paper currency validator of the present invention to energize either of the relay coils 888 or 890. Also, any "line cording" which appreciably affected the voltage supplied to the paper currency validator would cause the motor 562 to start operating in the reverse direction and would reset the COUNTERS 804 and 806.

Specifically, if "line cording" were to decrease the 24 volts, that normally is supplied to the cathode of Zener diode 304 in the MOTOR REVERSE LOGIC block 286, the twelve volts at the upper terminal of resistor 312 would not decrease until the voltage at the cathode of that Zener diode decreased to less than 12 volts. As the non-regulated 24 volts decreased to approximately 13 volts, the Zener diode 304 would become non-conductive, and hence the base of transistor 302 would tend to drop to ground voltage. Thereupon, that transistor would become non-conductive; and the voltage at the collector of that transistor would start to increase. Capacitor 329 which coacts with resistor 312 to constitute an RC network will retard the rate of increase of the collector voltage of transistor 302 and will thereby delay the application of a 1 to the input of inverter 314. This means that if the removals and re-insertions of the plug occurred at a rapid rate after the transistor 302 had become non-conductive, but before the voltage, that is applied to the paper currency validator, fell below the level which is needed to enable the various transistors and gates of that paper currency validator to function, the capacitor would maintain a 0 at the input of inverter 314 and thereby prevent a premature and un-needed reversal of the motor 562. In addition, the capacitor 329 will prevent premature and un-needed reversal of the motor 562 if a voltage transient, which otherwise might render transistor 302 non-conductive, were to develop.

If the removals and re-insertions of the plug occurred at a slower rate and thereby permitted a 1 to appear at the input of inverter 314, that inverter would apply a 0 to the cathode of diode 318 and to the uppermost inputs of NAND gates 728 and 730. Those NAND gates would apply 1's to the re-set input terminals of the COUNTERS 804 and 806 and would re-set those COUNTERS; and the diode 318 would become forward biased and thereby apply a 0 to the second lowermost input of NAND gate 326. The resulting 1 at the output of NAND gates 326 would effect the reversal of motor 562. All of this means that if "line cording" ever caused the twenty-four volts at the cathode of Zener diode 304 to decrease below 13 volts, transistor 302, inverter 314, and diode 318 would cause NAND gate 326 to initiate reversal of the motor 562 and to effect re-setting of the COUNTERS 804 and 806.

If the person who was attempting to "line cord" the paper currency validator of the present invention reinserted the plug in the socket before the voltage, that is applied to the paper currency validator, fell below the level which is needed to enable the various transistors and gates of that paper currency validator to function, the motor 562 would operate in the reverse direction. That motor would continue to operate in reverse, and the COUNTERS 804 and 806 would continue to remain re-set, until the switch 146 reopened as the inserted bill was moved back out of the bill transport 30.

In the foregoing description of a "line cording" attempt, it was assumed that the person re-inserted the plug before the voltage, which was applied to the paper currency validator, fell below the level which is needed to enable the various transistors and gates of that paper currency validator to function. If that person had waited until that voltage had fallen below that level and then re-inserted the plug, the voltages at the upper terminals of resistors 312 and 320 and at the cathode of Zener diode 304, in the MOTOR REVERSE LOGIC block 286 of FIG. 3A, would have been below 12 volts. As those voltages responded to the re-insertion of the plug to increase, the transistors 302 would remain non-conductive until the voltage at the cathode of Zener diode 304 reached 13 volts -- and, prior to that time, the voltage at the upper terminal of resistor 312 would apply a 1 to the input of inverter 314, and that inverter would again forward bias the diode 318 to again cause a 0 to be applied to the second lowermost input of NAND gate 326. Thereupon, the NAND gate would again effect reversal of the motor 562 and re-setting of the COUNTERS 804 and 806. It thus should be apparent that whether a person, who is attempting to "line cord" the paper currency validator, removes and re-inserts the plug rapidly or slowly, the transistor 302, the Zener diode 304, the resistors 306, 308, 312 and 320, the inverter 314, and the diode 318 will respond to that removal and re-insertion to cause a 0 to appear at the second lowermost input of NAND gate 326. At such time, the motor 562 will reverse and the COUNTERS 804 and 806 will be re-set.

If, in attempting to "line cord" the paper currency validator, a person left the plug out of the socket for more than eighteen seconds, the RC network, which is constituted by resistor 452 and capacitor 454 in the SPEED MAINTAINING sub-block 358 of FIG. 5 would have to be relied upon to re-start that motor. At the time that motor came to rest, in response to the "line cording," the NAND gate 251 would be applying a 1 to the interconnected inputs of NAND gate 434 in the SPEED MAINTAINING sub-block; and transistor 438 in that sub-block would be non-conductive, and NAND gate 448 would have a 1 applied to the upper input as well as to the lower input thereof. During the more than eighteen seconds while no power was being supplied to the paper currency validator, the capacitor 458 would discharge through resistor 460; and hence, when the plug subsequently was re-inserted in the socket, the NAND gate 450 would have a 0 at the input thereof. The resulting 1 at the output of that NAND gate would render transistor 466 conductive, and would thereby keep transistors 468, 480 and 482 and motor 562 non-conductive. If the 1 at the lower input of NAND gate 448 was continuous in nature, it would coact with the 1 which would re-appear at the upper input of that NAND gate, as the plug was re-inserted, to apply a 0 to the upper terminal of capacitor 458; and the resulting continuous 0 at the lower input of NAND gate 450 would keep the motor 562 de-energized. However, the 1 at the lower input of NAND gate 448 is not continuous in nature; and, for a few milliseconds after the plug would be re-inserted in the socket, the time constant of the RC network constituted by capacitor 454 and resistor 452, would leave a 0 at the upper terminal of that capacitor -- and hence at the lower input of NAND gate 448. The resulting 1 at the output of that NAND gate would permit capacitor 458 to charge and re-apply a 1 to the lower input to NAND gate 450 -- with consequent rendering of transistor 466 non-conductive and of transistors 468 and 480 and 482 and of motor 562 conductive. In this way, the resistor 452 and 454 make it possible to automatically re-start the motor 562 if a "line cording" attempt has caused that motor to remain de-energized for more than 18 seconds.

The resistor 452 and capacitor 454 also will be useful in automatically re-starting the motor 562 when a bill or other object is holding one of switches 146, 156 and 162 closed after a power interruption due to a storm or to the blowing of a fuse. Even though NAND gate 232, conductor 234, inverter 238, conductor 241, diode 245, NAND gate 251, conductor 253, NAND gate 434, transistor 438, and diode 444 will immediately re-apply a 1 to the upper input of NAND gate 448 as the power is restored, the resistor 452 and capacitor 454 will cause a 0 to be applied to the lower input of NAND gate 448 for a long enough time to permit capacitor 458 to re-charge, and thereby effect re-starting of the motor 562.

CONCLUSION

If desired, each of the FREQUENCY DETECTORS 792 and 794 could utilize a limiter, a tuned circuit and a threshold device of the type disclosed by Smith et al U.S. Pat. NO. 3,245,534; and that tuned circuit would have a fixed frequency which would enable that tuned circuit to respond to the spacing of the vertical grid lines on an authentic U.S. bill to supply four distinct signals to the threshold device. Alternatively, if desired, each of the FREQUENCY DETECTORS 792 and 794 could utilize a squaring circuit, a frequency-sensing circuit, and a threshold detector of the type disclosed by the said Fishel et al application; and that frequency-sensing circuit would have a fixed frequency which would enable that frequency-sensing circuit to respond to the spacing of the vertical grid lines on an authentic U.S. bill to supply four distinct signals to the threshold detector. However, in the said preferred embodiment of the present invention, phase locked loops are used in the FREQUENCY DETECTORS 792 and 794 -- despite the fact that the oscillators of phase locked loops can, and do, change the frequencies of the signals generated thereby during the normal operation of those phase locked loops, and despite the fact that the frequencies of the signals generated by the oscillators of the phase locked loops of the FREQUENCY DETECTORS are randomly in and out of phase with the signals applied to those phase locked loops. The present invention makes it possible to use phase locked loops used in the FREQUENCY DETECTORS 792 and 794 by equipping those phase locked loops with resistors and capacitors which closely limit the extents to which the center frequencies of the oscillators of those phase locked loops can shift, and also by applying the outputs of those FREQUENCY DETECTORS to counters which can validate bills that cause those FREQUENCY DETECTORS to provide numbers of counts which differ from the scheduled number of counts by just one count. Specifically, the present invention equips the phase locked loops of the FREQUENCY DETECTORS 792 and 794 with resistors and capacitors which limit the shifting of the center frequencies of the oscillators of those phase locked loops to plus or minus 5 percent of those center frequencies; and the COUNTERS 804 and 806 are made so they can validate bills which cause the magnetic heads 208 and 210, the amplifier 790 and either the FREQUENCY DETECTOR 792 or the FREQUENCY DETECTOR 794 to develop three and five, as well as four, time-spaced 0's. By using phase locked loops and COUNTERS rather than the limiters, the tuned circuits and the threshold devices of the said Smith et al patent or the squaring circuits, frequency-sensing circuits and threshold detectors of the said Fishel et al application, the present invention substantially reduces the size and the cost of the frequency-detecting portion of the circuit of the paper currency validator -- because the inductors of those tuned circuits and of those frequency-sensing circuits are bulky, and because the capacitors and inductors of those tuned circuits and of those frequency-sensing circuits must have precise values and must have low temperature coefficients, and hence are expensive. Moreover, the center frequencies of phase locked loops can easily be changed by adjustments in the positions of the movable contacts of shelf-type low temperature coefficient potentiometers. As a result, the speed of the motor 562 can be set to any desired value, and then the center frequencies of the phase locked loops in the FREQUENCY DETECTORS 804 and 806 can be set accordingly with ease and precision.

The BINARY COUNTER 254 in the TIMER block 244 and the various gates and inverters in the TIMER LOGIC block 262 provide digitally developed time intervals; and those time intervals are more precise than are the time intervals which can be developed by usual and customary RC networks. The 668 millisecond time interval which is provided by that BINARY COUNTER and NAND gate 268 is made substantially longer than the time interval which normally is required for an authentic U.S. bill to close switch 156 and then cause the appropriate FREQUENCY DETECTOR, NOR gate, COUNTER, NAND gate and inverter to cause the EXCLUSIVE OR gate 846 to apply 1 to conductor 850 and to cause converter 848 to apply a 0 to conductor 852. Specifically, when the contacts 808, 810, 820 and 822 in the VALIDATING AND VENDING LOGIC block 784 are in their lower positions, the EXCLUSIVE OR gate 846 should apply a 1 to conductor 850 and should cause inverter 848 to apply a 0 to conductor 852 approximately 472 milliseconds after the switch 156 was closed. However, when those contacts are in their upper positions, the EXCLUSIVE OR gate 846 should apply a 1 to conductor 850 and should cause inverter 848 to apply a 0 to conductor 852 approximately 532 milliseconds after the switch 156 was closed. The difference between the 668 milliseconds and the 532 milliseconds was provided to permit different speeds to be set for the motor 562 and, to a lesser extent, to compensate for variations in the amounts of travel of actuator 158 as it closes the switch 156.

The 535 millisecond time interval provided by BINARY COUNTER 254 and the NAND gate 270 is substantially longer than the 300 millisecond time interval which normally is noted between the closing of switch 156 and the closing of switch 162. However, that time interval was selected to permit different speeds to be set for the motor 562 and, to a lesser extent, to compensate for variations in the amounts of travel of the actuators 158 and 164, respectively, for the switches 156 and 162.

When the lower "runs" of the belt 198 and of its counterpart are moving at the rate of 10 inches per second, an authentic U.S. bill should close the switch 156 and then subsequently move beyond the actuator 158 of that switch, to permit re-opening of that switch, in less than the 735 milliseconds provided by the BINARY COUNTER 254 and NAND gate 272. However, that 735 millisecond time interval was selected to permit different speeds to be set for the motor 562 and, to a lesser extent, to compensate for variations in the amounts of travel of the actuator 158 as it closes, and then subsequently permits re-opening of, the switch 156.

Not only do the BINARY COUNTER 254 and the NAND gates 266, 268, 279 and 272 provide more precise timing than could any usual and customary RC network, but the time intervals which are provided by that BINARY COUNTER and NAND gates are virtually unaffected by changes in temperatures. Further, the size and cost of that BINARY COUNTER and of those NAND gates are less than the cost and size of such RC networks.

The BORDER sub-block 516 uses capacitor 712 and resistor 710 to provide a 60 millisecond time interval and uses capacitor 716 and resistor 714 to provide a 30 millisecond time interval. If desired, that BORDER sub-bock could be provided with a single sub-circuit which could provide a 90 millisecond time interval. However, the use of the two capacitors 712 and 716 and of the two resistors 710 and 714 has been found to be desirable from the point of view of cost and size.

The structure and circuit disclosed herein are especially adapted for use in the sensing of paper currency; but that structure and circuit could be used to sense documents and other suitably engraved or printed objects. Consequently, where used hereinafter in the claims, the word "bill" will be understood to comprehend paper currency, documents and other suitably engraved or printed objects.

To make a simulated bill which could be accepted by the paper currency validator of the present invention, a person would have to use a sheet of paper that had a length close to the length of an authentic U.S. bill, would have to provide a leading border which was generally similar to the leading border on an authentic U.S. bill, would have to provide four longitudinally spaced and laterally spaced groups of vertical lines that were in the same areas as the quadrants of the portrait background on an authentic U.S. bill, would have to provide intervals between the leading edges of the various lines in each of those groups of vertical lines which were essentially the same as the intervals between the leading edges of the various lines in the quadrants on an authentic U.S. bill, and would have to leave blank the area which is between four-tenths and five-tenths of an inch long and which immediately follows the leading border. Further, he would have to make the intensity of the magnetic material on that bill high enough to exceed the thresholds of transistor 682 in the BORDER sub-block 516 and of the phase locked loops in the FREQUENCY DETECTORS 792 and 794 and yet be low enough to be below the threshold level of the transistor 338 in the OVERLEVEL SENSING sub-block 296 of FIG. 7. As a result, any such person would have an exceedingly difficult, virtually impossible task.

Whereas the drawing and accompanying description have shown and described a preferred embodiment of the present invention, it should be apparent to those skilled in the art that various changes may be made in the form of the invention without affecting the scope thereof.

Claims

What we claim is:

1. A validator for documents which comprises a sensor that can respond to relative movement between itself and markings on a document to develop signals, means to provide relative movement between said sensor and said document to enable said sensor to respond to one group of markings on said document to develop a signal and to respond to another group of markings on said document to develop another signal, a sub-circuit which responds to the first said signal to develop an output signal at the end of a predetermined length of time after the termination of said first said signal if further markings are not sensed by said sensor within said predetermined length of time, a second sub-circuit which responds to said other signal to develop a second output signal, means responsive to the development of the first said output signal to enable utilization of said second output signal if the first said output signal is developed by the first said sub-circuit before said second output signal is developed by said second sub-circuit.

2. A validator as claimed in claim 1 wherein the first said sub-circuit includes a threshold detector, a timer and an output element, and wherein said output element can develop the first said output signal only when said threshold device does not receive signals from said sensor for a length of time controlled by said timer.

3. A validator as claimed in claim 1 wherein the first said sub-circuit includes an electronic "latch" which responds to the development of the first said output signal to become latched and thereby enables said first said sub-circuit to remain in its latched state even though a further signal is supplied to said first said sub-circuit.

4. A validator which comprises a sensor, means to provide relative movement between an authentic document and said sensor to enable said sensor to respond to markings on said authentic document to develop signals, a pattern detector which can develop a pattern signal as a given pattern, defined on said authentic document by some of said markings, is being sensed by said sensor, other of said markings on said document defining a border-like area which can cause said sensor to develop further signals, a sub-circuit that responds to said further signals which said sensor develops as said sensor senses said border-like area to develop a border signal, and means which responds to said border signal to enable utilization of said pattern signal, said means keeping said pattern signal from being utilized if said sub-circuit does not develop said border signal.

5. A validator which comprises a sensor, means providing relative movement between said sensor and a document, a detection circuit which can respond to the sensing of an authentic document of one type, a second detection circuit which can respond to the sensing of an authentic document of a second type, an inhibit circuit which can respond to a given signal to permit operation of said means but to inhibit the utilization of signals from said second detection circuit, and said inhibit circuit responding to a further signal to permit operation of said means but to inhibit the utilization of signals from the first said detection circuit.

6. A validator as claimed in claim 5 wherein said inhibit circuit responds to simultaneous application of said given signal and of said further signal to prevent operation of said means and also to inhibit utilization of signals from both the first said and said second detection circuits.

7. A validator which comprises a magnetic sensor, means to provide relative movement between said magnetic sensor and a document, a reversing circuit which responds to actuation thereof to cause said means to reverse and thereby return said document to the person who inserted it, a switch that responds to the insertion of a document to initiate actuation of said means, a threshold device which responds to signals from said magnetic sensor to determine whether the intensity of the magnetic material in the ink on said document is great enough to be comparable to that on an authentic document, and a second threshold device which will determine whether the amount of magnetic material in the ink on said document appreciably exceeds the amount on an authentic document, and said reversing circuit responding to a signal from said second threshold device or to the absence of a signal from the first said threshold device to become actuated and to reverse said means, and further means connecting the outputs of said threshold devices to said reversing circuit.

8. A validator for documents which comprises a sensor that can sense markings on a document to develop signals, said sensor responding to one group of markings on said document to develop one signal and responding to another group of markings on said document to develop another signal, a subcircuit which responds to said one signal to develop an output signal but which delays the developing of said output signal for at least a predetermined minimum length of time after the termination of said one signal, a second sub-circuit which responds to said other signal to develop a utilizable output signal, and means which will enable utilization of said utilizable output signal only if the first said output signal is developed by the first said sub-circuit before said utilizable output signal is developed by said second sub-circuit, whereby said utilizable output signal will not be utilized if said sensor develops said other signal during the sensing of a document which does not have a group of markings thereon in position to be sensed by said sensor before said sensor senses said other group of markings.

9. A validator which comprises a sensor, a second sensor, means to provide relative movement between said sensors and a document, the first said sensor being mounted to consecutively sense two spaced-apart areas on said document during said relative movement of said document and said sensors, said second sensor being mounted to engage two further spaced-apart areas on said document during said relative movement of said document and said sensors, at least one of said two spaced-apart areas on said document being physically in register with at least one of said two further spaced-apart areas on said document, and said sensors being spaced longitudinally relative to each other to enable said sensors to develop time-spaced sequential signals during the sensing of said one areas which are physically in register with each other.

10. A validator which has a plurality of sensors that are disposed to sense different areas on a document, said sensors being spaced longitudinally relative to each other to enable said sensors to coact with said different areas on said document to provide a plurality of signals which are spaced apart in time, means providing a given signal only if it receives said plurality of signals in time-spaced relation, one of said sensors sensing two spaced-apart areas on said document to develop two time-spaced signals, and said other of said sensors developing a signal during the time space between said two time-spaced signals which said one sensor develops.

11. A validator which has a plurality of sensors that are disposed to sense different areas on a document, said sensors being spaced longitudinally relative to each other to enable said sensors to coact with said different areas on said document to provide a plurality of signals which are spaced apart in time, means providing a given signal only if it receives said plurality of signals in time-spaced relation, a sub-circuit that will develop an output signal in response to the signals which are developed when said sensors sense given areas on a document of one type, a second sub-circuit that will develop a second output signal in response to the signals which are developed when said sensors sense given areas on a document of a second type, and a third sub-circuit that will effect rejection of any document which causes the first said sub-circuit and said second sub-circuit to develop the first said and said second output signals simultaneously.

12. A validator which has a plurality of sensors that are disposed to sense different areas on a document, said sensors being spaced longitudinally relative to each other to enable said sensors to coact with said different areas on said document to provide a plurality of signals which are spaced apart in time, means providing a given signal only if it receives said plurality of signals in time-spaced relation, a sub-circuit that will develop an output signal in response to the application thereto of signals having a predetermined frequency, a second sub-circuit that will develop a second output signal in response to the application thereto of signals having a different predetermined frequency, and a third sub-circuit that will effect rejection of any document which causes the first said sub-circuit and said second sub-circuit to develop the first said and said second output signals simultaneously.

13. A validator which has a plurality of sensors that are disposed to sense different areas on a document, said sensors being spaced longitudinally relative to each other to enable said sensors to coact with said different areas on said document to provide a plurality of signals which are spaced apart in time, means providing a given signal only if it receives said plurality of signals in time-spaced relation said sensors being connected in series with one another, said series-connected sensors being connected to the input of an amplifier, said sensors successively applying consecutive but time-spaced signals to said amplifier, and said amplifier amplifying said consecutive time-spaced signals from said sensors.

14. A validator which comprises a sensor, means to provide relative movement between said sensor and a document, an accept circuit, an inhibit circuit that is adapted to keep said accept circuit from developing an accept signal, and a signal sensing circuit which responds to signals developed by said sensor and which causes said inhibit circuit to inhibit said accept circuit if said signal-sensing circuit receives signals from said sensor while said sensor is sensing the area between predetermined spaced areas on said document.

15. A validator which has a "line cording" circuit that comprises a selectively conductive device, an output sub-circuit that is connected to the output of said selectively conductive device, and an input sub-circuit that is connected to the input of said selectively conductive device, said input sub-circuit being connectable to a suitable voltage, said output sub-circuit being connectable to a lower voltage, said suitable voltage and said lower voltage responding to prolonged removal of power from said "line cording" circuit to decrease, and a voltage-dropping element in said input sub-circuit, said voltage-dropping element normally applying a voltage to the input of said selectively conductive device which will tend to hold said selectively conductive device in one state but said voltage-dropping element responding to reductions in said suitable voltage which can occur as power is removed from said "line cording" circuit to apply a different voltage to said input of said selectively conductive device which will cause said selectively conductive device to change to a different state, said voltage-dropping element applying said different voltage to said input of said selectively conductive device before any effective decrease could occur in said lower voltage as power is removed from said "line cording" circuit, and said selectively conductive device remaining in said different state if said lower voltage effectively decreases and continuing to remain in said different state until said lower voltage returns to its normal level.

16. A validator as claimed in claim 15 wherein a source of voltage provides said suitable voltage and said lower voltage, and wherein said lower voltage is a regulated voltage.

17. A validator as claimed in claim 15 wherein a source of voltage provides said suitable voltage, and wherein said lower voltage is a regulated voltage developed from said suitable voltage.

18. A validator which comprises a first sensor, a second sensor, means to provide relative movement between a document and said sensors along a predetermined path, said sensors being displaced transversely of said path and also being displaced longitudinally relative to each other along said path, said first sensor responding to said relative movement between itself and said document to successively sense two longitudinally spaced areas on said document to provide two time-displaced signals, said second sensor responding to said relative movement between itself and said document to successively sense two further longitudinally spaced areas on said document to provide two further time-displaced signals, the longitudinal displacing of said sensors relative to each other enabling said first sensor to sense one of the first said longitudinally spaced areas on said document before said second sensor senses the first of said further longitudinally spaced areas on said document enabling said first sensor to sense the second of the first said longitudinally spaced areas on said document after said second sensor senses the first of said further longitudinally spaced areas on said document, and enabling said second sensor to sense the second of said further longitudinally spaced areas on said document after the first sensor senses the second of the first said longitudinally spaced areas on said document, and means to sense and respond to the signals developed by the first and second sensors as the first said longitudinally spaced areas on said document and said further longitudinally spaced areas on said document are sensed.

19. A validator as claimed in claim 12 wherein said means includes a counter which receives said time-displaced signals and counts same.

20. A validator as claimed in claim 18 wherein said time-displaced signals have frequencies, and wherein a phase locked loop operates as a frequency detector to determine whether said frequencies are within the pass band established by said phase locked loop.

21. A validator which comprises a sensor, means that provides relative movement between said sensor and a document, said sensor responding to an authentic document to provide a predetermined signal, position-sensing means which develops a positional signal when a predetermined positional relationship occurs between said position-sensing means and said document, a timer that includes a pulse source and a counter, said timer responding to said positional signal from said position-sensing means to cause said counter to start counting, and means that will develop a non-accept signal if said position-sensing means is still providing said positional signal but said sensor has not provided said predetermined signal prior to the time the count in said counter reaches a predetermined value.

22. A validator which comprises a first position-sensing means, a second position-sensing means, means that provides relative movement between said first and said second position-sensing means and a document, said first position-sensing means developing a first positional signal when a predetermined positional relationship occurs between said first positional-sensing means and said document, said second position-sensing means developing a second positional signal when a predetermined positional relationship occurs between said second position-sensing means and said document, a timer that includes a pulse source and a counter, said timer responding to said first positional signal from said first position-sensing means to cause said counter to start counting, and means that will develop a non-accept signal if said first position-sensing means is still providing said first positional signal and if said second position-sensing means is not providing said second positional signal at the time the count in said counter reaches a predetermined value.

23. A validator which comprises a position-sensing means, means that provides relative movement between said position-sensing means and a document, said position-sensing means providing a positional signal when a predetermined positional relationship occurs between said position-sensing means and said document, a timer that includes a pulse source and a counter, said timer responding to said positional signal from said position-sensing means to cause said counter to start counting, and means that will develop a not-accept signal if said position-sensing means is still providing said positional signal at the time the count in said counter reaches a predetermined value.

24. A validator which comprises sensing means to sense a document and provide a predetermined number of separate and distinct signals, a counter which receives and counts said signals, said counter providing an output signal if the number of counts provided by said sensing means in response to the sensing of a given document equals, or differs by one from, said predetermined number of signals, said counter having a plurality of output terminals, said output terminals having a first state when said validator is at rest, said counter progressively changing said output terminals to a second state as said counter responds to said signals to count up to a pre-set number, said counter thereafter responding to further of said signals to progressively change said output terminals back to said first state, said output signal from said counter being developed as the second of two of said output terminals is changed to said second state, and said output signal from said counter being terminated as the first of said two of said output terminals is changed back to said first state.

25. A validator which comprises sensing means to sense a document and provide a predetermined number of separate and distinct signals, a counter which receives and counts said signals, said counter providing an output signal if the number of counts provided by said sensing means in response to the sensing of a given document equals, or differs by one from, said predetermined number of signals, said counter having a plurality of output terminals, said output terminals having a first state when said validator is at rest, said counter progressively changing said output terminals to a second state as said counter responds to said signals to count up to a pre-set number, said counter thereafter responding to further of said signals to progressively change said output terminals back to said first state, said output signal from said counter being developed as the second of two of said output terminals is changed to said second state, said output signal from said counter being terminated as the first of said two of said output terminals is changed back to said first state, and switch means connected to said output terminals to permit changing of said pre-set number, and thereby permit changing of the output terminals which are said two output terminals.

26. A validator for documents which comprises sensing means that can respond to relative movement between itself and markings on an authentic document to develop a signal having a predetermined frequency, means to provide relative movement between said sensing means and said document, and a phase locked loop which receives said signal and which responds to said signal to develop an output signal, said phase locked loop not responding to a signal from said sensor which has an appreciably different frequency.

27. A validator as claimed in claim 26 wherein said document has a plurality of areas thereon that are sensed by said sensing means, wherein said sensing means responds to said plurality of areas to develop a plurality of signals having said predetermined frequency, wherein said phase locked loop responds to said plurality of signals having said predetermined frequency to develop a plurality of output signals, wherein a counter receives and counts said plurality of output signals, and wherein said counter will provide an output signal if the number of output signals from said phase locked loop equals, or differs by one from, from a pre-set number.

28. A validator which has a pair of magnetic heads, means to provide relative movement between said magnetic heads and a document having a plurality of patterns thereon which are spaced apart by an intervening area, said magnetic heads being spaced apart in a direction which corresponds to the direction in which said plurality of patterns are spaced apart from each other, one of said magnetic heads being positioned to sense one of said patterns and thereby effect the development of a signal, the other of said magnetic heads being positioned to sense the other of said patterns and thereby effect the development of a second signal, the spacing apart of said magnetic heads disposing said other of said magnetic heads in register with said intervening area whenever said one of said magnetic heads is in register with said one of said patterns and disposing said one of said magnetic heads in register with said intervening area whenever said other of said magnetic heads is in register with said other of said patterns, whereby the air gaps of said magnetic heads can not simultaneously engage both of said patterns and whereby said magnetic heads will respond to said relative movement to provide time-spaced signals.