Converter Drive Circuit In An Electronic Timepiece

Abstract

A converter drive circuit in an electronic timepiece movement, which provides pulses of adjustable pulse width to a drive coil of an electro-mechanical converter of the timepiece movement, to thereby generate an induced voltage in the coil and thus drive the time-piece. The drive circuit is designed so as to be able to sense the oscillation amplitude of the converter in terms of electrical voltage, and increase the pulse width of the drive pulses fed to the coil in an abruptly and stepwisely way when an outside mechanical disturbance is applied to the timepiece movement in the reducing sense of the induced voltage in the drive coil.

Description

BACKGROUND OF THE INVENTION

This invention relates generally to improvements in and relating to electronic timepieces. It relates more specifically to improvements in the drive circuit adapted for driving the electro-mechanical converter, such as drive balance wheel, tuning fork, tuning lead or the like time-keeping drive means in the above kind of timepiece, especially crystal quartz type electronic watch.

In the electronic timepiece, it is necessary to convert electrical signals fed from a time base signal source into a corresponding movement to be transmitted to the time-display means.

In the case of the resonance converter where a resonator such as balance wheel, tuning fork, tuning lead or the like member is forcedly driven with a series of time base frequency signal pulses delivered from a time-base signal source such as crystal quartz oscillator, it is requisitely necessary to keep the oscillation amplitude of the converter within a specifically selected range for transmitting the corresponding movements thereof through the gear train to the time-display means of the timepiece for accurate operation thereof.

In the case of forced drive of the resonance converter of the above kind, the amplitude and phase of the oscillatory movements thereof are maintained substantially constant by the voltage, current, frequency and pulse width of the input signal fed in the form of a series of regular pulses.

As is commonly known, however, the timepiece movement will be influenced frequently and adversely by unavoidable and disturbing outside mechanical disturbances such as shocks, thereby disturbing the steady, regular and stabilized time-keeping operation of the timepiece movement.

It has been already proposed that for stabilizing the time-keeping movements of the timepiece against outside mechanical disturbances such as shocks, by varying intentionally the pulse width of the forced drive input voltage signal in response to the thus invited variation in the oscillation amplitude of the converter of the above kind, and indeed, by the provision of an amplitude controller for modifying the width of the input pulses responsive to the amplitude variation.

According to the prior technique, however, the variation of the width of the input drive voltage pulses is carried into effect in a continuous way in response to the disturbed variation of the oscillation amplitude of the resonator, thereby a quick and rapid recovery of the regular oscillation mode to acquire a quicker response in the corrective control operation.

It is a further drawback of the conventional arrangement serving for the above service represents a highly complicated design, especially of the wave shaper and the amplitude controller contained therein.

SUMMARY OF THE INVENTION

The object of the present invention is to provide an amplitude control circuit of simple design, yet capable of operating in a quickly responsive manner.

A further object of the invention resides in the provision of the amplitude control circuit of the above kind, capable of dispensing with otherwise necessary amplitude detecting or sensing coil means.

BRIEF DESCRIPTION OF THE DRAWINGS

These and further objects, features and advantages of the present invention will become more apparent as description proceeds by reference to the accompanying drawings illustrative of several preferred embodiments of the invention.

In the drawings:

FIG. 1 represents a schematic connection diagram substantially represented in blocks, of a preferred embodiment of the invention, representing an electro-mechanical converter usable in an electronic watch.

FIG. 2 is a circuit diagram illustrative of a detector or sensor contained in the circuit arrangement shown in FIG. 1.

FIG. 3 is a circuit diagram of an input switcher including an AND- and a NOR-circuit and contained in the circuit arrangement shown in FIG. 1.

FIG. 4 is a circuit diagram of a converter drive circuit contained in the circuit arrangement shown in FIG. 1.

FIGS. 5 and 6 are two equivalent circuits of that shown in FIG. 4 combined with FIG. 2.

FIG. 7 shows several signal wave curves appearing at several places of the circuit arrangement shown in FIG. 1 under its steady and regular operating conditions.

FIG. 8 is a similar view to FIG. 7, wherein, however, an amplitude reducing outside disturbance such as a mechanical shock is applied to the timepiece movement.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the accompanying drawings, especially FIG. 1 thereof, numeral 1 represents schematically, an oscillator adapted for delivery of a series of electrical pulses of precisely constant amplitude and frequency, such as, for instant, a quartz crystal oscillator although not limitative. The frequency may be 32.768 kc, as an example.

As seen, a resistor 101 is connected across the crystal oscillator 1 for feedback purpose. The output from the crystal oscillator 1 is fed to a conventional inverter 2, the design thereof being similar to that shown in FIG. 2 at 13. These elements 1, 2 and 101 constitute in combination a crystal oscillator circuit.

The output from the circuit 102' is fed alternatively to the one or another input of first flip-flop 5 through second and third inverters 3 and 4. Output terminals 6 and 7 of the first flip-flop 5 are connected through a plurality of similar flip-flops, not shown, to the input terminals 8 and 9 of a first main flip-flop 10 of similar design, the number of frequency dividing flip-flop stages arranged between two section lines X-X' and Y-Y' depending upon occasional demands and having been omitted from the drawing only for simplicity. The input frequency at these input terminals 8 and 9 may be 128 Hz. Further second and third main frequency dividing flip-flops 11 and 12 are connected in series to the first one 10 as shown.

Numeral 13 is a amplitude detector circuit, to be more specifically described hereinafter by reference to FIG. 2, the output side of said detector being connected electrically through a terminal "A" to one of two inputs of a state memory circuit, preferably a flip-flop. The remaining input of the state memory circuit 14 is connected through a lead 104 to one of the output terminal 102 of the third main flip-flop 12. As will be more fully described hereinafter, when the output of the detector 13 is fed to the memory 14, the latter is set to "0," while the output, denoted with "P3," of the last stage flip-flop 12 is fed to the memory 14, the latter is set to "1."

The output of the memory 14 is connected through a terminal "B" to one of the two inputs of AND-gate 15. The remaining input of the latter is connected through a lead 105 to a terminal 106 which is provided between the first and second main flip-flops 10 and 11.

One of the inputs of the first main flip-flop 10 is connected through flip-flops 11 and 12 a lead 104, memory circuit 14 and AND-gate 15 to one of the inputs of a NOR-gate 16, the input of the latter being connected through a lead 110 with the output of AND-gate 15. The remaining input of NOR-gate 16 is connected through a lead 109 with the said input terminal 9.

NAND-gate 17 has four input terminals 111, 112, 113 and 114. The first input terminal 111 is connected with another output terminal 103 of the third main flip-flop stage 12 through a lead 115. The second input terminal 112 is connected through a lead 117 with a terminal 116 which is provided in one of two connecting routes between the third and four main flip-flops 11 and 12.

The third input terminal 113 is connected through a lead 108 with a terminal 107 inserted in one of two connecting routes between the first and second main flip-flop stages 10 and 11.

The fourth input 114 is connected through a terminal "C" with the output of NOR-gate 16 which constitutes an input switching circuit 30 in combination with AND-gate 15.

Numerals 18 and 19 denote respective inverters, the output of NAND-gate 17 is connected through a terminal "D" and lead 120 to one of two inputs of the first inverter 18. The remaining input of this inverter 18 is connected with a positive voltage source, only schematically shown at "V," say 1.5 volts. One of two outputs of this inverter 18 is earthed as shown, while the remaining output is connected through terminal 118, coil 20 and terminal 119 to the output of the second inverter 19. One of two inputs of this inverter 19 is earthed as shown, while the remaining input is fed back through lead 122 to the terminal 118.

Input of the amplitude detector 13 is connected through lead 121 and terminal "E" to said terminal 119. Inverters 18 and 19, coil 20 and terminals 118 and 119 are shown more specifically in FIG. 4. Coil 20 is arranged to drive an electro-mechanical converter such as a balance wheel of a timepiece, although not specifically shown only for simplicity.

When the input pulses fed to the input terminals 8 and 9 have a frequency of 128 Hz, these inputs being denoted with P0 and P0, respectively, as shown in FIG. 1, the output frequency at the output terminals 107 and 106 of the first main flip-flop 10, and represented by P1 and P1, respectively, must have a frequency of 64 Hz. In the similar way, a frequency of 32 Hz will appear at the outlets of the second main flip-flop 11, the outputs therefrom being denoted with P2 and P2, respectively. It will be seen that the outputs, P3 and P3 shown at the output terminals 102; 103, must have a frequency of 16 Hz.

The amplitude detector circuit is shown more specifically in FIG. 2. This detector 13 comprises P-channel MOS-transistor 131 and N-channel MOS-transistor 132 connected in a complementary manner as shown. "E" represents input terminal, while "A" represents output terminal as referred to hereinbefore.

In FIG. 3, the input switching circuit 30 is more specifically shown. The AND-gate 15 comprises transistors 301; 304; 305 and 306, while the NOR-gate 16 comprises transistors 301; 302; 303 and 306. Transistors 301; 303 and 304 represent P-channel MOS-transistors, while transistors 302; 305 and 306 are N-channel MOS-transistors. In these logic circuits 15 and 16, input signal, P0, is aPplied to terminal 122; output signal from first main flip-flop 10, p1, is applied to terminal 123; and output signal from memory circuit 14 is applied to terminal 124 through terminal "B."

In FIG. 4, the drive circuit 40 is more specifically shown, as comprising N-channel MOS-transistors 401 and 403; and P-channel MOS-transistor 402. Inverter 18 comprises transistors 401 and 402, while inverter 19 comprises the remaining transistor 403. At input terminal "V," the source voltage is applied. With this arrangement, the source voltage "V" does not appear at output terminal "E," when there is no input signal at the terminal "D."

FIG. 5 is an equivalent circuit of the circuit arrangement shown in FIG. 4 combined with FIG. 2 when input signals are not applied to the amplitude detector 13, and inverters 18; 19, while an equivalent circuit shown in FIG. 6 is obtained, when these input signals are applied.

In FIG. 7, a series of voltage curves are shown when the electro-mechanical converter, preferably a electro-magnetically driven balance wheel of an electronic watch, not shown, is operating under regular and undisturbed conditions.

The uppermost voltage curve 51' represents the voltage induced in the drive coil 20. The straight line 52 represents the amplitude detecting voltage level, while numeral 53 represents a corresponding current wave form supplied to the same drive coil 20. Further voltage curves can be easily understood by reference to the corresponding explanatory symbols given at the left side of the drawing.

In FIG. 8, corresponding voltage curves are shown, however, in the case of a reduction in amplitude appeared in the balance wheel of the watch. In this case, the voltage 51a induced in the coil 20 is lower than the amplitude detecting voltage level 52.

Now, it is assumed that a series of regular pulses of 16 Hz, 1/16 period pulse width, is applied as a forcingly synchronizing signal to the drive coil 20 and the electronic timepiece movement is working under its regular and undisturbed working conditions, various voltage signals, FIG. 7, will appear at several places of the whole circuit arrangement so far shown and described hereinbefore.

Although not shown on account of its very popularity among those skilled in the art, the drive coil 20 is arranged to cooperate electromagnetically with permanent magnets fixedly mounted on the balance wheel. The induced voltage curve 51 in the drive coil 20 is the results of such electromagnetic cooperation. At 51' and 51", the induced voltage attains its maximum value. These maximum voltages are induced twice in the drive coil 20 during a complete angular oscillation of the balance wheel, when the latter has its maximum moving velocity by attaining a full overlap with the magnet.

By proper design of the electromagnetic converter, it is possible to generate a forced drive force when the induced voltage in the drive coil 20 attains at the peak value 51". In the drive circuit proposed by the present invention, the induced voltage peak 51' is utilized for the desired amplitude detection.

It is further possible to set the threshold voltage of each of the inverters 18; 19 of the detector circuit 40 shown in FIGS. 1 and 2 to about 0.75 volt, with the source voltage V be set to 1.5 volts, while the peak values of the induced voltage in drive coil 20 is set to 1.0 - 1.2 volts under regular working conditions. Under these conditions, the induced voltage will take the curve shown at "L" in FIG. 7, as a representative example. In this case, the detecting voltage level 52 will be 0.75 volt. This voltage corresponds to the threshold voltage of the detector circuit (comparator) 13 and is the reference voltage for comparison with the induced voltage in the drive coil. This peak voltage 51' will cross the level line 52 at points a and b, respectively. Thus, in the course of this interval 2-b, P-channel MOS-transistor 131 of the detector circuit 13 will be off, while N-channel MOS-transistor 132 will be on. In otherwise period, the transistor 131 is on, while the transistor 132 is off. Thus, output voltage appearing at terminal "A" will be as at 54 in FIG. 7.

When the output at terminal "B" of memory circuit 14 (shown by voltage curve 56) is set to "0" at the trailing edge b of this pulse, and the terminal 124 for the input switching circuit 15; 16 has "0"-input, P-channel MOS-transistor 304 is on while N-channel MOS-transistor 305 is off, and thus, the output P1 at terminals 106; 123 can not pass through AND-gate 15 of the input switching circuit block 30, while the input P0 appearing at terminals 9; 122 can pass therethrough block 30. One of the inputs (110) of NOR-gate 16 has a zero input, while the input terminal is applied through 122 with P0; thus the output from NOR-gate 16 becomes P0 by inverting the input P0. Therefore, an output same as P0 will appear at output terminal "C," as shown by a voltage curve 57 in FIG. 7.

Thus, voltage input P0 will appear at an input terminal 114 to NAND-gate 17; P1 at terminal 113; P2 at 112; and P3 at 111, as shown in FIG. 7 by respective wave curves 58, 59 and 60. In this way, a series of pulses as shown by wave curve 61, FIG. 7, having a frequency of 16 Hz, will appear at the output terminal D. The pulse width amounts to one-sixteenth of the period.

Under the steady and regular operating conditions of the converter, such as a drive balance wheel, wherein the induced voltage 51', FIG. 7, exceeds the detection level 52, the forcingly synchronizing input 61 has a predetermined frequency of 16 Hz and a pulse width of one-sixteenth period. Memory circuit 14 is impressed with reset pulses in the form of P3 and reset to "1" upon each application of a drive pulse, thereby returning its state to that appearing in advance of the application of set pulse at input terminal "A." It will thus be understood that for each oscillation of the converter, its amplitude in terms of voltage is compared with the detection level voltage at 52.

When the oscillation amplitude of the converter should be reduced by unintentional application of an outside mechanical shock or the like disturbing force to the converter, as may be frequently encountered during personal carriage of the timepiece, preferably watch, thereby the induced voltage as at 51a in the drive coil 20 becoming a lower value than the detection level 52 (refer to FIG. 8), transistor 131 will turn to on, while transistor 132 becomes off. Therefore, no output pulse will appear at the output terminal "A." Thus, no set pulses will be applied to memory circuit 14 and on the contrary, reset pulses, P3 will alway be applied. The circuit 14 is always reset to "1" and the output appearing at "B" is of "1" of the binary logic. From this reason, the P-channel MOS-transistor of the input switching circuit, FIG. 3, will be off, while the N-channel MOS-transistor thereof will be on. The pulse series P1 can therefore pass through the AND-gate 15 the output appearing at "C" being of the wave form at 62, representing: (P0 + P1). This output is applied to the input terminal 114 or (0) to NAND-gate 17. Input P1 of the wave form 58 will be applied to the input terminal (1) or 113; P2 of wave form 59 to (2) or 112; and P3 of wave form 60 to (3) or 111. In this way, at the output terminal "D" will appear an output pulses 61a, FIG. 8, representing a pulse width of one-eighth amplitude for each thereof. In this case, a series of drive current pulses in the form of the curve 53a will flow through the coil 20, and the relationship thereof relative to the induced voltage 51a may be that which is shown in FIG. 8. As a result, the input is doubled and the disturbingly reduced amplitude of the converter will be rapidly corrected towards its state inherent to the steady and regular operational conditions of the converter.

Although the foregoing description has been directed substantially to the case of use of a drive balance wheel as a resonance converter, it will be clear from the foregoing that the invention can equally be applied to any other kind of electro-mechanical converter, such as, for instance, tuning fork, tuning lead or the like.

In the description of the foregoing embodiment, the synchronizing input pulses to the converter has been set to 16 Hz and a pulse of one-sixteenth amplitude. As was referred to hereinabove, in the case of reduction of the oscillation amplitude, the pulse width was increased to one-eighth of the amplitude. This can be generalizedly expressed that the pulse width is set to 1/2.sup.n (n being an integer such as 1, 2, . . .) which means that in the case of reduction in the oscillation amplitude, the pulse width may be increased to twice, triple, quadruple of the original and so on, by proper modifications of the whole circuit arrangement as may easily occur to any person skilled in the art, upon being guided by the novel teachings of the present invention so far shown and described. It will be also conceivable that the drive pulse frequency should not be limited to 16 Hz.

As is easily understood from the foregoing, a superior advantage of the present invention resides in such that in the case of reduction in the oscillation amplitude to that lower than the detection level, the drive pulse width is automatically increased, in the above specific embodiment, to a doubled value, towards quicker recovery to the steady and regular oscillation of the converter, so as to invite a stabilized operation of the converter, upon occasional invitation of an outside mechanical disturbance, such as outside shocks.

A further advantage resides in that for the time being upon initiation of the switching-in operation of the electronic timepiece movement, the width of each of successive drive pulses fed to the drive coil as at 20 is doubled of the regular and steady one, so as to attain rather quickly and automatically the destined stabilized oscillation of the converter. In this way, the development in the oscillatory movement of the resonance converter can be highly accelerated to the destined one adapted for the desired time-keeping purpose, thus attaining a very shortening of a time lag which extends between the switching-in and the regular time-keeping operation.

A still further advantage resides in such that an independent maximum value of the forced synchronizing phase of each oscillative movement and in the course of a voltage curve corresponding to an oscillation of the converter is utilized for the desired purpose, and thus, a specifically provided coil means for sensing the oscillation amplitude could be dispensed with.

A still further advantage resides in the following.

When the induced voltage in the drive coil is utilized for the amplitude control and with use of the source-earthed type drive circuit, the induced voltage must be overlapped with the source voltage, and thus, a d.c. -cut condenser is generally used. In this case, this kind of condenser may have preferably its capacity in the order of 0.5 microfarad (.mu.F) which fact invites generally a substantial difficulty in the realization of the overall MOS-lization and thus in a larger dimensioning of the circuit arrangement than otherwise and a miniaturization thereof would become difficult to realize. In this case of the embodiment of drive circuit shown in FIG. 4, however, with no signal applied, only N-channel MOS-transistor 401 is on, while P-channel MOS-transistor 402 and N-channel MOS-transistor 22 are off. As shown in FIG. 5, one end "F" of the drive coil 20 is earthed and the opposite end "G" is connected with inlet terminal "E" of the amplitude detector circuit, and thus, only the induced voltage in the drive coil is applied to the said input terminal "E." In the case of application of signal, N-channel MOS-transistor 401 is off and P-channel MOS-transistor 402 and N-channel MOS-transistor 403 are on, so as to earth the coil end terminal "G." Therefore, the drive circuit becomes as shown in FIG. 6 wherein the source voltage is cut off. Thus, only the induced voltage in the drive coil is utilized for amplitude detection purpose. In this way, the overall MOS-lization can be realized with easiness for realization of a miniatured circuit.

It is a final advantage that although the circuit arrangement is highly simple in its design and provide a composite service, yet consuming a specifically added power to the conventional one. It is therefore easily understood that the circuit arrangement proposed by the present invention is highly valuable for use in electronic watches, especially crystal quartz type watches for the conversion service of the above kind.

Claims

The embodiments of the invention in which an exclusive property or priviledge is claimed are as follows:

1. A converter drive circuit in an electronic timepiece movement comprising:

a time base signal source for providing a series of first output pulses of predetermined amplitude and frequency;

a plurality of interconnected frequency dividers for successively frequency-dividing said first output pulses and providing corresponding consecutively differing divided-frequency pulsed signals at the outputs of said frequency dividers thereof;

wave-shaping means connected with a predetermined number of said outputs of said frequency dividers for receiving and processing said divided-frequency pulsed signals and providing a first drive pulsed signal of predetermined pulse width to a first control terminal of a drive coil of an electro-mechanical converter of the timepiece movement to generate an induced voltage therein to operate the movement successively under regular operating conditions;

switching means connected between said wave-shaping means and a predetermined number of said outputs of said frequency dividers;

sensing means coupled at a first input to a second terminal of said drive coil, at a second input to at least one output of the said frequency dividers and at its output to said switching means, said sensing means sensing the oscillation amplitude of said converter in terms of said induced voltage at said drive coil and comparing the latter with the input threshold voltage level of the said sensing means to provide a first indication signal when said induced voltage is above said threshold voltage and a second indication signal when it is lower, whereby under normal operating conditions of said timepiece movement said switching means operates in response to said first indication signal to permit passage therethrough of chosen ones of said divided-frequency pulsed signals necessary to thereby generate said first drive pulsed signal at said wave-shaping means of predetermined pulse width, and when an outside disturbance is applied to the timepiece movement in the reducing sense of said induced voltage in said drive coil, said switching means operates in response to said second indication signal to permit passage therethrough of additional necessary ones of said divided-frequency pulsed signals so that a required second drive pulsed signal of adjusted pulse width over said predetermined pulse width, is provided at said wave-shaping means and supplied to said drive coil to correct for said disturbance and restore regular operating driving oscillations to said timepiece movement.

2. A converter drive circuit in an electronic timepiece movement as set forth in claim 1, wherein said predetermined width is adjusted to at least double the value thereof when the outside mechanical disturbance is applied.

3. A converter drive circuit in an electronic timepiece movement as set forth in claim 1, wherein said sensing means comprises an amplitude detector for making said comparison of the induced voltage with the said threshold voltage of the sensing means voltage.

4. A converter drive circuit in an electronic timepiece movement as set forth in claim 3, wherein said sensing means further comprises a memory circuit for storing the output of said amplitude detector in the binary mode.

5. A converter drive circuit in an electronic timepiece movement as set forth in claim 4, wherein said wave-shaping means comprises a NAND-circuit, and said switching means comprises a combination of an AND-circuit with a NOR-circuit.

6. A converter drive circuit in an electronic timepiece movement as set forth in claim 5, further comprising a drive circuit of said drive coil having a pair of inverters one of which is connected between said NAND-circuit and the first terminal of the drive coil, while the other inverter is connected between said first and second terminals in a feedback path.