Nonconductive Data Link Control Apparatus

Abstract

Apparatus provides a nonconductive data link between command and response locations remote from each other for accomplishing substantially proportional control and includes safety features to prevent outside interference.

Description

BACKGROUND OF THE INVENTION

In certain situations, it is desirable to control the operation of responsive devices such as hydraulic actuators from a remote command location in such a way that there is no conductive connection between the control mechanism and the responsive device.

For example, a workman may be physically located on the platform of an aerial lift while working on high voltage lines and he desires to control the operation of the lift to change his position. It is important that there be no electrically conductive connection between the control mechanism which he manipulates on the platform and the actuators which move the lift. Such an arrangement is shown in United States Pat. No. 3,136,385 where the nonconductive link is preferably provided by light control, although other modes of communication such as electromagnetic waves, infrared, microwaves, and ultrasonic waves are mentioned. However, the teaching of the disclosure of said U.S. Pat. No. 3,136,385 is on-off control.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide substantially proportional control, as opposed to on-off control, by means of a nonconductive data link between a command location and a remote response location.

The primary objective is to provide such a nonconductive data link which has safety features to prevent unintentional interference or operation of the controlled actuators. More specifically, besides providing no electrical connection between the operator and the actuator, the data sending means includes station code means, and the data accepting means includes means for identifying the station code and means for decaying the signal in case the station code is not recognized.

Preferably, the nonconductive data link of the present invention employs an FM radio control system having multiple channels. A battery operated FM transmitter that is small enough for convenient shoulder-strap carrying is employed. Manually operated control units provide analog control positions. The transmitter contains data digitizing and multiplexing circuitry that samples each channel a predetermined number of times per second, such as about twenty times per second. A unique digital station code is added to each data sample and transmitted with the FM signal. This station code eliminates the possibility of false control from radio noise or other nearby transmitters.

The nonconductive data link also includes a receiver which is a small, conveniently mounted unit that is powered from the vehicle or equipment electrical system. It contains signal processing circuitry that decodes the transmitted digital information. An amplifier is provided for each channel to drive the pilot stage of a conventional proportional type electrohydraulic flow control servovalve.

While an FM radio control system is preferred, it is to be understood that other suitable data sending and accepting means may be employed, such as other radio, light or sound waves.

Typical applications where safe, wireless control may be required include utility service vehicles, power line construction and repair vehicles, equipment operating in a hazardous environment, industrial vehicles, hoists, conveyors and the like, loading and unloading type vehicles, automatic material handling equipment, cranes for shipboard loading and unloading, and mobile equipment operating with a reduced crew.

Other objects and advantages of the present invention will be apparent from the following detailed description of a preferred embodiment taken in conjunction with the accompanying drawings.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the preferred data sending means constructed in accordance with the present invention and shown operatively associated with analog control position means.

FIG. 2 is a diagram of the cycle format for one complete cycle of such data sending means.

FIG. 3 is a diagram of the station identification format relative to the clock interval, including provision for synchronization and parity, for such data sending means.

FIG. 4 is a diagram of the control data format relative to the clock interval for such data sending means.

FIG. 5 is a wave diagram of the timing clock means shown in FIG. 1.

FIG. 6 is a wave diagram of a typical station code produced by the station code generator shown in FIG. 1. FIG. 7 is a wave diagram of typical control data.

FIG. 8 is a wave diagram of the output of the master synchronous commutator or multiplexer.

FIG. 9 is a wave diagram of the output of the non-return to zero converter shown in FIG. 1.

FIG. 10 is a block diagram of the preferred data accepting means which receives the data from the data sending means illustrated in FIG. 1, and showing such data accepting means operatively associated with proportional type electrohydraulic servovalves which control the flow of fluid with respect to hydraulic actuators.

FIG. 11 is a wave diagram of the output of the radio frequency receiver means shown in FIG. 10 and represents typical control data.

FIG. 12 is a wave diagram for a phase locked timing clock means shown in FIG. 10.

FIG. 13 is a wave diagram indicating recovered digital data, representing typical control data bytes, the output of the return to zero data converter shown in FIG. 10.

FIG. 14 is a wave diagram of the synchronization control signal output of the synchronization detector shown in FIG. 10.

FIG. 15 is a wave diagram for a hold control signal, one of the outputs of the synchronous commutator or multiplexer shown in FIG. 10.

FIG. 16 is a representation of parallel paths for control information fed to the hold circuits shown in FIG. 10, another of the outputs of said synchronous commutator or multiplexer.

FIG. 17 is a diagram representing direct current output for one channel from one of the digital-to-analog converters shown in FIG. 10.

FIG. 18 is a diagram representing direct current output for another channel from another of the digital-to-analog converters shown in FIG. 10.

FIG. 19 is a diagram representing a plot of system direct current output signals against direction and extent of control motion inputs.

FIG. 20 is another wave diagram for the phase locked timing clock or slave clock means shown in FIG. 10.

FIG. 21 is a wave diagram representing a typical station code signal and depicting an error therein, as fed to the station code comparator shown in FIG. 10, another output from the synchronous commutator or multiplexer.

FIG. 22 is another wave diagram depicting hold control pulses emanating from the synchronous commutator or multiplexer.

FIG. 23 is a wave diagram depicting a reset to zero pulse in the event of an error, the output of the station code comparator shown in FIG. 10.

FIG. 24 is a diagram depicting direct current output for channel (1) corresponding to byte 5 depicted in FIGS. 11, 13, 16, and 17.

FIG. 25 is a diagram depicting direct current output for channel (2) corresponding to byte 6 depicted in FIGS. 11, 13, 16, and 18 and illustrating the effect of the reset to zero signal of FIG. 23 on current level, this being the signal output from current decay to zero circuit shown in FIG. 10.

FIG. 26 is a representation of parallel paths for control information illustrating the effect of the reset to zero signal of FIG. 23 on signals such as those illustrated in FIG. 16.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Apparatus embodying a preferred form of the present invention provides substantially proportional control at a response location remote from a command location through a non-conductive data link. Such apparatus is shown as comprising data sending means illustrated in FIG. 1 and producing wave forms illustrated in FIGS. 2-9 at various places within such sending means, and also comprising data accepting means illustrated in FIG. 10 and producing wave forms illustrated in FIGS. 11-18, and 20-26, at various places within such accepting means ultimately to produce in any channel any of the direct current levels as depicted in FIG. 19 and substantially proportional to command input and utilized to energize the torque motor of an electrohydraulic servovalve which controls the flow of fluid with respect to a hydraulic actuator.

Referring to FIG. 1, the data sending means 20 is in the form of am FM radio transmitter which receives analog control position inputs from controllers. Such control devices may be of any suitable type such as a manually controlled potentiometer having a pivoted control lever or a rotatable control knob, and may be provided in any desired number from 1 to n, although eight such devices to provide eight channels is preferred. In FIG. 1, the controller for channel 1 is designated 21, that for channel 2 as 21', and that for channel n as 21".

The data sending means 20 is shown as including a synchronous selector commutator or multiplexer 22, an analog-to-digital converter 23, a master synchronous commutator or multiplexer 24, a station code generator 25, a parity generator 26, a synchronization code generator 28, a timing clock means 29, having a frequency (f), a non-return to zero converter 30, a frequency shift modulator 31, a high frequency oscillator 32, an RF amplifier 33, and an antenna 34.

Arrowed lines connecting the various elements 21-34 represent signal flow. Thus, lines 35, 35', 35" extend from controllers 21, 21', 22", respectively, to synchronous selector commutator or multiplexer 22. An analog signal flows via line 36 to analog-to-digital converter 23. The signal from this converter flows via line 38 to master synchronous commutator or multiplexer 24. Additional inputs to multiplexer 24 are represented by line 39 from station code generator 25, by line 40 from synchronization code generator 28, and by line 41 from parity generator 26 which also receives a signal from multiplexer 24 via line 42. Synchronism between multiplexers 22 and 24 is achieved by an input control signal flowing via line 43 from multiplexer 24 to multiplexer 22. Multiplexer 24 also receives a timing signal from timing clock means 29 via line 44. This timing signal is also fed to non-return to zero converter 30 via line 45. This converter 30 receives an output signal from multiplexer 24 via line 46. The output signal from converter 30 flows via line 48 to frequency shift modulator 31 which receives via line 49 a RF carrier frequency from oscillator 32. The output signal from modulator 31 flows via line 50 to RF amplifier 33 and from the latter to antenna 34 via line 51.

The timing clock means 29 typically has a frequency of 2 kilohertz or 2000 bits per second. The cycle format for one complete cycle is depicted in FIG. 2 wherein a digital word comprises 12 bytes, the first four of which are allocated to station identification and the last eight of which are allocated for control data and severally constitute the eight channels of data. Thus, there are 96 bits per word and about 20.8 words per second. Each bit is about one-half millisecond duration and each byte about 4 milliseconds duration.

The station identification format relative to clock interval is depicted in FIG. 3. As there shown for each identification byte, the first two bits are allocated for synchronization, the third bit for parity, and the remaining five bits for station identification, the latter being provided according to a binary code. Thus, in byte 1 the five station identification bits are designated 2.sup.0, 2.sup.1, 2.sup.2, 2.sup.3, 2.sup.4, the similar bits for byte 2 are designated 2.sup.5, 2.sup.6, 2.sup.7, 2.sup.8, 2.sup.9, and so on for bytes 3 and 4. Thus 20 binary encoded bits are provided which will permit more than one million station code identifications.

The control data format relative to clock interval is depicted in FIG. 4. As there shown for each control data byte the first two bits are allocated for synchronization, the third bit for parity, the fourth bit for sign, and remaining four bits for control data or output current, the latter being designated 2.sup.3, 2.sup.2, 2.sup.1, and 2.sup.0 in each such bit. This allows a maximum current level of 15 to be indicated. As previously stated, one control data byte is allocated for each channel.

The control data byte for each channel (bytes 5-12) comprises a binary digital signal to represent an analog signal in the range of from 0 to 15 increments, besides its sign or polarity, synchronization and parity. Parity is an on or off pulse to give an even number of bits. Sign or polarity is also an on or off pulse to represent the direction of command movement, leaving four binarily determined pulses to indicate the magnitude of the analog signal. Thus, for example, a 3 volt analog signal could be represented by a pulse at slot 2.sup.0 (representing 1) and one at slot 2.sup.1 (representing 2), the sum of which would be 3. As another example, if a 12 volt analog signal were commanded, a pulse would appear at slot 2.sup.2 (representing 4) and at slot 2.sup.3 (representing 8), the sum of which would be 12.

The cyclic rate or clock interval of the timing clock means 29 is depicted in FIG. 5. This clock interval is transmitted via lines 44 and 45. The frequency of clock 29 is typically 2 kilohertz, making the clock interval equal to one-half millisecond.

A portion of typical station code is depicted in FIG. 6 in which byte 1 has three pulses for station code, two pulses for synchronization and one pulse for parity, and in which byte 2 has two pulses for station code, two pulses for synchronization and no pulse for parity since the byte already has an even number of bits. The station code is transmitted via line 39.

Typical control data for two bytes (bytes 5 and 6) are depicted in FIG. 7. In byte 5, there is zero control command for the channel represented by such byte and therefore zero current is produced. Since two pulses for synchronization occur and this is an even number, there is no parity pulse. As for byte 6, there are pulses at the last three bits representing 2.sup.2, 2.sup.1, and 2.sup.0, or the values 4, 2 and 1, or the sum of 7, or 7/15, or a control command producing approximately 47 percent of maximum direct current. This signal is carried via line 38.

The master synchronous commutator or (multiplexer) combines station code, digital commands, parity and synchronization into a composite signal format as shown in FIGS. 2, 3 and 4. A digital representation of typical station code and control data bytes is shown by FIGS. 6 and 7. The output waveform of multiplexer 24 on line 46 is shown in FIG. 8. A digital "1" present in FIGS. 6 and 7 is represented in FIG. 8 by a high voltage level during the entire timing clock interval. Likewise a digital "0" is represented by a zero voltage level. Thus FIG. 8 shows a high voltage level for the first two clock intervals, representing two digital 1's that occur during the first two timing clock intervals of data byte 5.

The output of master commutator 24, line 46 in FIG. 1, is combined with the timing clock output on line 45 in the non-return to zero converter 30. The purpose of this combination is twofold, namely (a) to reduce the number of signal transitions associated with transmitting the digital information, and (b) to have the signal transitions occur intermediate the clock cycle rather than at the start thereof. The output of the non-return to zero converter on line 48 is shown by FIG. 9. This waveform makes a change of state (transition) at the falling edge of each timing clock waveform if the output of the master commutator is at a high voltage level. This transition represents a digital 1. If the waveform on line 46 is at a low voltage level, no change occurs in the output of the non-return to zero converter. Thus, a digital 1 is represented by a change in state, or transition, in the output of the non-return to zero converter, and a digital 0 is represented by no change in state intermediate the timing clock cycle. The signal in line 48 depicted in FIG. 9 is used to drive the frequency shift modulator 31 and vary the RF carrier frequency to produce an FM signal amplified at 33 and radiated to the atmosphere via antenna 34.

Referring to FIG. 10, the data accepting means 60 is in the form of a FM radio receiver which receives digital signal control inputs and converts them to substantially proportional direct current levels for each channel, utilized for a given channel to energize the coil of an electrical force motor of a proportional type electrohydraulic flow control servovalve 61 which meters fluid flow with respect to a hydraulic actuator 62 which produces an output motion represented typically by the broken line 63. A proportional type electrohydraulic flow control servovalve is provided for each channel (severally designated 1, 2 --n) and may be of any suitable type such as shown, for example, in United States Pats. Nos. 3,023,782. Likewise, the hydraulic actuator 62 for each servovalve may be of any suitable type, such as a piston and cylinder device as depicted schematically operatively associated with the servovalve disclosed in said U.S. Pat. No. 3,023,782. The output motion 63 of such actuator 62 may be rectilinear or rotary or otherwise, depending upon the specific nature of the actuator. The operative association between a servovalve 61 and its actuator 62 are represented by the pair of fluid conduits 64 and 65.

For channel (2), the servovalve is indicated at 61', the hydraulic actuator at 62', the hydraulic conduits at 64' and 65', and the axis motion for this channel at 63'. For channel (n), the servovalve is indicated 61", the hydraulic actuator at 62", the hydraulic conduits at 64" and 65", and the axis motion for this channel at 63".

The data accepting means 60 is shown as including an omnidirectional antenna 66, an RF receiver 68, a frequency shift detector 69, a return to zero data converter 70, a synchronous commutator or multiplexer 71, a phase locked timing clock or slave means 72, a synchronization detector 73, a hold circuit 74 for each channel, a digital-to-analog converter and current amplifier 75 for each channel, a current decay to zero circuit 76 for each channel, a station code comparator 78, and a parity check comparator 79. The hold circuits for channels (2) and (n) are indicated at 74' and 74", respectively; the digital-to-analog converters and current amplifiers for channels (2) and (n) are indicated at 75'0 and 75", respectively; and the current decay to zero circuits for channels (2) and (n) are indicated at 76' and 76", respectively.

Arrowed lines connecting the various elements 66-79 represent signal flow. The RF receiver 68, connected to antenna 66 by a line 80, and frequency shift detector 69 are shown connected together by a line 81 jointly provide a radio receiver the output signal from which flows via line 82 to return to zero converter 70.

This output signal is also fed via branch line 83 to phase locked timing clock or slave means 72 which produces a clock rate or frequency (f) of 2 kilohertz, in the example being considered. The output clock rate signal is fed via line 84 to return to zero data converter 70, via branch line 85 to synchronization detector 73, and via another branch line 86 also to synchronous commutator or multiplexer 71.

The output signal of return to zero data converter 70 flows via line 88 to synchronous commutator or multiplexer 71, and also flows via branch line 89 to synchronization detector 73. The output signal of this detector is fed via line 90 to synchronous commutator or multiplexer 71.

Control information in parallel from the synchronous commutator or multiplexer 71 is entered into each hold circuit 74 and is represented by the signal flow line 91. Lines 91' and 91" represent the signal flow lines for channels (2) and (n), respectively. A hold control signal from the same multiplexer can flow via a line 92 to each hold circuit 74. Branch lines 92' and 92" feed this hold control signal into the hold circuits 74' and 74", respectively, for channels (2) and (n).

Any signal from any hold circuit 74 flows via line 93 to the corresponding digital-to-analog converter and current amplifier 75. The output signal from this converter and amplifier flows via line 94 to the corresponding current decay to zero circuit 76, and the output signal from this circuit flows via line 95 to the coil of the corresponding electrohydraulic servovalve 61. The corresponding signal flow lines for channels (2) and (n) are indicated at 93', 94', 95' and 93", 94", 95", respectively; the digital-to-analog converters and current amplifiers for channels (2) and (n) are indicated at 75' and 75", respectively; and the current decay to zero circuits for channels (2) and (n) are indicated at 76' and 76", respectively.

An output signal from the synchronous commutator or multiplexer 71 flows via line 96 to parity check comparator 79, and also flows via branch line 98 to station code comparator 78. Any output in the form of a reset to zero signal in line 99 from station code comparator 78 can be fed via line 100 into hold circuit 74 and also via line 101 into current decay to zero circuit 76. Branch lines such as indicated at 100' and 100" from line 100 can feed the same signal into the hold circuits 74' and 74" for the other channels. Similarly, branch lines such as indicated at 101' and 101" from line 101 can feed the same signal into current decay to zero circuits 76', 76" for the other channels.

Any output signal from parity check comparator 79 in the form of a reset to zero signal is fed by a flow line 102 into lines 100, 100', 100" and into lines 101, 101', 101", and hence into hold circuits 74, 74', 74" and current decay to zero circuits 76, 76', 76".

FIG. 11 is a wave form representing the output of frequency shift detector 69. It is the same signal as in the line 48 of the transmitter and depicted in FIG. 9.

FIG. 12 illustrates the clock cycle or interval of the phase locked timing clock 72 in output signal flow line 84 and has the same wave form as for the timing clock 29 depicted in FIG. 5, the frequency being the same.

FIG. 13 is a waveform of the recovered digital data flowing in line 88 into synchronous commutator or multiplexer 71 and is similar to the wave form shown in FIG. 7.

FIG. 14 represents the signal waveform in output line 90 from synchronization detector 73. The waveform has a pulse at the beginning of each byte.

FIG. 15 represents the wave form for the hold control signal in each of lines 92, 92', and 92". This hold control signal is a pulse produced near the end of each byte, establishing a point in time and functions to enter and hold the digital information entering via lines 91, 91', and 91" for the various channels.

The digital information is conveyed along five parallel signal paths for the control data bytes successively. This is depicted in FIG. 16 for bytes 5 and 6 shown in FIGS. 11 and 13. Referring to FIG. 16, the top four of the five paths depicted represent the binary encoded control data, severally designated 2.sup.0, 2.sup.1, 2.sup.2, 2.sup.3, for each byte successively, and the fifth representing the sign for the corresponding byte.

The hold control signal effect on the five paths shown in FIG. 16 is also related to the hold control signal indicated in FIG. 15. Thus, the left half portion of FIG. 16 represents byte 5 depicted in FIGS. 11 and 13, and the right half portion of FIG. 16 represents byte 6 depicted in FIGS. 11 and 13. More specifically, there is zero control data for byte 5 and therefore no pulses in the path lines in the left half portion of FIG. 16; whereas in the right half portion the control data represented by the pulses 2.sup.2, 2.sup.1, and 2.sup.0 in FIG. 13 are represented by pulses in the correspondingly designated paths of FIG. 16. Thus the control data for each of bytes 5 through 12, severally representing eight channels, is fed successively along the parallel paths depicted in FIG. 16 as long as a synchronization pulse (FIG. 14) and a hold control pulse (FIG. 15) are produced for each control data byte.

The digital-to-analog converters and current amplifiers 75, 75', and 75" for the various channels convert and amplify the respective signals received through lines 93, 93', and 93" for each channel and pass them on via the corresponding output lines 94,94', and 94". The direct current output will be substantially proportional to the binary encoded control data. This is illustrated in FIG. 17 for channel or axis (1) where the direct current output is zero for byte 5. For byte 6 which corresponds to channel or axis (2), the direct current output is about 47 percent of maximum, as illustrated in FIG. 18.

In this connection, reference is made to FIG. 19 wherein motion in one direction of any of controllers 21, 21', 21" (FIG. 1) represents forward control motion to the right of a vertical ordinate and is divided into 15 steps; and motion of such controller in an opposite direction represents vertical control motion to the left of such ordinate and is also divided into 15 steps. In FIG. 19, servovalve coil current is plotted along the vertical ordinate, that above the horizontal ordinate being positive in polarity and that below being negative.

Assuming the current decay to zero circuits 76, 76', and 76" are inoperative at the moment, the direct current outputs in lines 94, 94', and 94" will be transmitted through lines 95, 95', and 95" into the corresponding coils of the electrohydraulic servovalves 61, 61', and 61" and act as electrical command signals therefor. Thus, the system output is capable of producing 30 current levels, besides zero, resulting in 30 velocities of motion.

Let us assume now that an error in code is detected. The effect of this is depicted in FIGS. 20 - 26.

FIG. 20 repeats again the clock cycle or interval of the phase locked timing clock 72 as shown in FIG. 12.

FIG. 21 represents a typical station code in line 98 such as indicated for bytes 1 and 2 as depicted in FIG. 6, except that an error in code is indicated in byte 2 in FIG. 21. The effect of this error in code will now be traced.

FIG. 22 represents a hold control signal produced near the end of each of bytes 1 and 2, and as a pulse signal is similar to that represented in FIG. 15.

FIG. 23 represents the reset to zero signal in output line 99 from station code comparator 78. When the station code compares correctly there is no reset to zero pulse produced, absent in the left half portion of FIG. 22 for byte 1, but a pulse is produced when the station code comparator indicates an error in code, such pulse being a reset to zero pulse indicated for byte 2 in FIG. 23. This pulse is conducted by lines 100, 100', 100" into hold circuits 74, 74', 74", and via lines 101, 101', 101" into current decay to zero circuits 76, 76', 76".

FIG. 24 represents the direct current output control to channel (1) in line 94 or 95, the current level being zero.

FIG. 25 represents the direct current output control to channel (2) in line 94', indicated previously in FIG. 18 at about 47 percent maximum level, until reset to zero pulse depicted in FIG. 22 becomes effective to cause the current in line 94 to be decayed to zero over a brief period of time by circuit 76' so as to eliminate a control signal for servovalve 61' in line 95'.

FIG. 26 illustrates the effect on assumed control information produced by the reset to zero signal. Assuming there had been a pulse in paths 2.sup.0, 2.sup.1, and 2.sup.2 of FIG. 26 so as to represent control data, the reset to zero pulse depicted in FIG. 22, has the effect of terminating these pulses at the time of the reset to zero pulse as depicted in FIG. 26.

While the effect of a reset to zero signal in line 99 from station code comparator 78 has been illustrated and described, similar effects would have been produced if parity check comparator 79 had produced a reset to zero signal in line 102.

From the foregoing, it will be seen that an operator manipulating any one or more of controllers 21, 21', 21" produces an analog control position signal for each channel, which is read cyclically about 20 times per second, is converted to a digital signal encoded with station identification and parity, transmitted from one location by FM radio to a remote location where the radio signal is timed, synchronized, checked for station identification and parity, converted from a digital to analog signal but monitored by circuits which will either hold a channel open or decay a current in a given channel in the event an error is detected in station identification or parity, all to the end of producing substantially proportional direct current levels utilized to command electrohydraulic servovalves which control actuators that do work at such remote location in proportional response to the command manipulators at the transmitting location. The nub of the inventive concept is to provide a nonconductive data link incorporating safeguards to prevent unintentional interference between command and response.

The various electrical and electronic components named and discussed herein above are well known to those skilled in the art and therefore require no more specific description.

Claims

What is claimed is:

1. Nonconductive data link control apparatus for providing substantially proportional control of actuation means at a remote location, responsive to analog commands from a command location, comprising binary data sending means including pulse coding means responsive to said analog commands, digital station code means, sending multiplexer means for sequencing the pulse outputs of said pulse coding means and said station code means, means for producing a transmission carrier and binary modulation means responsive to said pulse outputs for digital modulation of said carrier only between two discrete states, and binary modulated carrier accepting means including station code comparator means, pulse code to analog data conversion means and means controlled by said comparator means to control operation of said conversion means to provide a control signal for said actuation means.

2. Apparatus according to claim 1 wherein said binary data sending means includes a radio transmitter, said transmission carrier is a radio frequency, and said binary modulated carrier accepting means includes a radio receiver.

3. Apparatus according to claim 1 wherein said binary data sending means includes a non-return to zero converter operatively interposed between said sending multiplexer means and said binary modulation means, and said binary modulated carrier accepting means includes a return to zero converter.

4. Apparatus according to claim 1 wherein said binary data sending means includes parity generator means, and said binary modulated carrier accepting means includes parity check means.

5. Apparatus according to claim 1 wherein said data conversion means includes decay to zero means.

6. Apparatus according to claim 1 wherein said binary data sending means includes sending timing clock means for controlling said sending multiplexer means, and said binary modulated carrier accepting means includes accepting multiplexer means for distributing the digital inputs to said station code comparator means and said pulse code to analog data conversion means and accepting timing clock means for controlling said accepting multiplexer means, whereby a signal is transmitted by said binary data sending means on a regular basis to synchronize the frequencies of said sending and accepting timing clock means.