Character Generation Display System

Abstract

Character generation circuitry for an alpha-numeric cathode ray tube display wherein successive characters appear in successive character slots of a plurality of text lines, the top segments of the characters being formed on a first pass and successively lower segments being formed in subsequent passes. The system includes delay line circuitry for providing pulses corresponding in time to a plurality of horizontal increments for each horizontal trace passing through a character slot, the delay line circuitry working in combination with logic which designate selected ones of the horizontal increments according to designations of the horizontal trace and character then being formed. The logic circuits are so arranged that the same logic is used in forming similar character portions where they appear in different characters.

Description

REFERENCE TO RELATED APPLICATION

This invention relates to the disclosure of application Ser. No. 806,472 filed Mar. 12, 1969.

The invention relates to display systems and, while not limited thereto, relates particularly to an alpha-numeric display system for use in computer terminal systems.

Computer terminal equipment generally refers to the equipment remotely located relative to the main computer assembly. For example, a stockbroker may have a desk top unit connected to the main computer assembly by telephone lines so that information such as current price quotations or background data for a corporation can be requested by means of a keyboard and, the requested data received from the computer can be displayed on a cathode ray tube. Corporate executives can be similarly equipped to obtain up-to-date inventory, sales, or customer data. Instantaneous cathode ray read-out is preferable to print-out systems in many cases but, to date, systems capable of producing substantial quantities of data on an instantaneous read-out have not been readily available.

The existing high density, high quality, instantaneous display systems capable of producing 2,000 or more alpha-numeric characters are exceedingly costly and, as a result, cannot be economically justified in many installations where substantial read-out information is desired. The display systems of more moderate cost severely sacrifice the character display capability or character definition of both and often present display distortions disturbing to the viewer.

The general object of this invention is to provide a moderate cost, high density, display system with negligible distortion.

In the system according to the invention, the scanning sequence consists of successive horizontal traces by means of an electron beam which gradually moves from the top to the bottom of the display, much the same as in a conventional television scanning pattern. A horizontal line of characters, referred to as a text line, is formed by a plurality of adjacent horizontal traces, twenty horizontal traces per text line having been found to provide excellent character definition. The top segments of each of the characters of a text line are formed during the first pass and successively lower segments are formed on subsequent passes. A horizontal line is divided up according to the number of characters on the line appearing in successive character slots and each character slot is then further divided into horizontal increments, 24 horizontal increments per character having been found to produce excellent character definition. However, there can be considerable variation in the number of successive traces and horizontal increments which are used in making up the characters acceptable to the viewer.

The character designations for a text line are stored in a recirculating register which advances at a rate synchronous with the passage of the electron beam through successive character slots. Prior to entry of the electron beam into a character slot, the logic circuits in the system designate selected ones of the horizontal increments according to the designation for the character and horizontal trace then being formed. A delay line receives a pulse each time the horizontal trace enters a new character slot and, in response, provides successively delayed pulses corresponding in time to the successive horizontal increments. The pulses are supplied to gate circuits so that gates associated with the preselected horizontal increments are enabled to pass the respectively delayed pulses to thereby obtain the appropriate signal for application to the grid of the cathode ray electron beam.

Many characters have configurations which, in part, are the same. For example, the left side straight portion is common to upper case letters B, D, E, F, H, K, L, M, N, P, and R and upper and lower rounded portions are common to the letters C, G, O and Q. The logic circuits, according to the invention are so designed that portions of characters, in effect, can be removed and other portions substituted to thereby greatly reduce the quantity of logic circuitry required to select the proper ones of 480 possible increments per character (assuming 24 horizontal increments and 20 lines per character) in each of the 70 or more different characters which may be found in a complete system.

The number of characters which can be displayed on a complete display frame is increased according to the invention by a unique multiple beam scanning arrangement and a non linear vertical deflection.

An illustrative embodiment of the invention is set forth in the following more detailed specification. The specification includes the drawings wherein:

FIG. 1 is a diagram illustrating the general character display layout for a three beam system;

FIG. 2 is a schematic diagram showing a three beam cathode ray tube according to the invention;

FIGS. 3A-3C are wave forms for the vertical deflection;

FIGS. 4A-4C illustrate formation of the letters "O," "C" and "G," respectively;

FIGS. 5A-5C illustrate the various control signals for the electron beam as required for the formation of the displays and FIGS. 4A-4C, respectively;

FIG. 6 is a block diagram illustrating the overall control logic for the system;

FIG. 7 is a schematic diagram of the character generation logic and related circuits utilized in the formation of the letters, "O" "C," and "G," as illustrated in FIGS. 4A-4C and 5A-5C; and

FIG. 8 illustrates the manner in which the even and odd fields are interlaced.

ORGANIZATION OF DISPLAY

The organization of the alpha-numeric display on the viewing screen is shown in FIG. 1 for a three gun cathode ray system using a tube generally as shown in FIG. 2. The cathode ray tube includes an evacuated glass envelope 1 having a phosphor coated surface 2 inside the tube at the enlarged viewing end 3. The electron guns designated A, B and C, respectively, are located within the tube at the end opposite the screen. The three guns are vertically aligned and oriented so that the respective beams cross at point 5 in the center of the vertical and horizontal deflection yokes 4. The vertical orientation of the guns is such that trace A produced by gun A forms the first text line on the screen, while trace B from electron gun B forms the second text line and trace C from electron gun C forms the third text line, as indicated in FIG. 1. Thus, traces A, B and C are actually quite close together, the actual spacing corresponding to the relative spacing of adjacent text lines.

In the illustrative embodiment each text line consists of 20 successive horizontal traces. The upper 16 traces are used in the formation of upper case letters and numerals, and the lower four lines are utilized to form the stems of lower case letters such as f, g, j, p, q and y. The horizontal sweep frequency is 15.75 kilohertz and, therefore, the time allocated for a horizontal trace is 64 microseconds. The control logic for the system divides the horizontal sweep into 128 character slots and, hence, the individual characters appear at a rate of 2.016 megahertz. It is necessary to provide time for return of the electron beam from left to right following each horizontal sweep and therefore only approximately 100 of the 128 characters are actually used.

After the formation of the first text block consisting of three successive text lines, the vertical deflection signal drops all three beams simultaneously to a position where they form the second text block likewise consisting of three text lines. Successive text blocks are then formed in similar fashion. Since there are 20 horizontal traces per text line and a total of 525 horizontal traces forming a complete frame for each gun, there is a total possibility of 26 text blocks. However, in order to provide sufficient time for vertical retrace of the electron beams, at least one of the text blocks would be lost. A complete frame consisting of 525 lines per electron gun is provided 30 times per second. To reduce flicker of the display, all of the odd lines are provided first to form an odd field and then all of the even lines are formed to provide an even field. Each field consists of 262.5 lines and a vertical scan from top to bottom of the screen occurs at the rate of 60 times per second.

The manner in which the interlace is achieved is shown generally in FIG. 8, which for simplicity only shows the scanning pattern for one of the beams. The first line begins in the upper left corner and moves to the right under control of the horizontal sweep and also moves downwardly slightly under influence of the vertical sweep. Successive parallel lines 2-262 are then formed gradually moving down the screen, these being referred to as odd lines of the odd field even though numbered consecutively in FIG. 8. Line 263 is split between the bottom and top of the scanning pattern. In other works, line 263 reaches the bottom of the pattern half way through the horizontal trace, at which time the vertical sweep circuit returns the beam to the top of the pattern. The second half of line 263 therefore is located just above the right portion of line 1. The next line, line 264, is midway between lines 1 and 2. Successive lines of the even field are interlaced between lines of the odd field in similar fashion. After another 262.5 lines a total of 525 lines will have been completed and the beam is in the lower right corner of the scanning pattern at which time the vertical and horizontal sweep circuits return the beam to the upper left corner to begin a new frame. The first text line (following the line numbering system in FIG. 8) would consist of lines 1-10 of the odd field and lines 164-273 of the even field.

The vertical sweep signal is shown in FIG. 3A having a fundamental frequency of 60 hertz and being in the form of a linear ramp signal repeatedly going from negative to positive. The 60 hertz fundamental frequency corresponds exactly to the formation of 262.5 horizontal traces on the screen. Superimposed upon the vertical sweep signal is a diddle sweep signal as shown in FIG. 3B. The diddle sweep is a linear ramp signal, going repeatedly from positive to negative. The period of each ramp signal corresponds exactly to the time required for the formation of 10 horizontal traces, this being the horizontal traces of a text line formed during either the odd or even field. The diddle sweep is synchronized with the formation of the text lines and the period of each ramp signal is therefore 640 microseconds. The effect of the combined sweep signal as shown in FIG. 3C is to reduce the slope of the vertical sweep for the duration of each text line. The amplitude of the diddle sweep signal adjusted to reduce the slope by somewhat more than a factor of three to thereby compress the horizontal traces making up a text line into a space somewhat less than a third of that otherwise occupied. The number of horizontal traces making up a text line remains the same and, therefore, even though the character becomes smaller, there is no material sacrifice in character definition. By compressing the text lines in this fashion, space is provided for text lines provided by the other electron guns of the system.

The manner in which the individual characters are produced is illustrated in FIGS. 4A-4C and 5A-5C. In these figures the capital letters "O," "C" and "G" are formed on grids consisting of 16 vertically separated traces designated Y.sub.1 -Y.sub.16 with each horizontal trace broken into 24 horizontal increments designated X.sub.1 -X.sub.24. The electrical signals applied to the grid of the electron gun for forming the letter "O" are shown in FIG. 5A and the resulting visible display is shown in FIG. 4A. Similarly, the electrical signals for the letters "C" and "G" are shown in FIGS. 5B and 5C, respectively, and the resulting displays are shown in FIGS. 4B and 4C.

During the first horizontal trace Y.sub.1 in FIGS. 5A, the electron gun is off during increments X.sub.1 to X.sub.7, is on during increments X.sub.8 to X.sub.17 and is off during increments X.sub.18 to X.sub.24. The result is the upper visible segment b as shown in FIG. 4A. During the second horizontal trace Y.sub.2 the beam is off during increments X.sub.1 -X.sub.5, X.sub.10 -X.sub.15 and X.sub.20 -X.sub.24, but is on during increments X.sub.6 -X.sub.9 and X.sub.16 -X.sub.19 to provide the upper segments c shown in FIG. 4A. On the third horizontal trace Y.sub.3 the beam is off during segments X.sub.1 -X.sub.4, X.sub.9 -X.sub.16, X.sub.21 -X.sub.24 and is on during segments X.sub.5 -X.sub.8 and X.sub.17 -X.sub.20 to provide the upper segments d; during the fourth horizontal trace Y.sub.4 the electron beam is off during segments X.sub.1-X.sub.3, X.sub.8 -X.sub.17 , X.sub.22 -X.sub.24 and is on during segments X.sub.4 -X.sub.7 and X.sub.18 -X.sub.21 to provide the upper segments c; and during the fifth horizontal trace the electron beam is off during segments X.sub.1 -X.sub.2, X.sub.7 -X.sub.18 and X.sub.23 -X.sub.24 and is on during segments X.sub.3 -X.sub.6 and X.sub.19 -X.sub.22 to provide the upper segments f. During horizontal traces Y.sub.6 through Y.sub.11 the beam is off during segments X.sub.1, X.sub.6 -X.sub.19 and X.sub.24 to provide the sections a shown in FIG. 4A. The lower segments b-f in FIG. 4A are formed during the 12th through 16th horizontal traces Y.sub.12 -Y.sub.16.

As will be described hereinafter in greater detail, the upper and lower curved portions of the letter "O" i.e. segments b-c, are formed by one set of logic circuits and the vertical portions, i.e., segments a and f, are formed by another set of logic circuits. The two portions are combined, as shown in the illustration at the bottom of FIG. 4A to form the letter "O."

FIG. 4B shows the visible display for the letter "C," and FIG. 5B shows the corresponding electrical signals applied to the grid of the electron gun to form the letter "C." The letter "C" is formed in a fashion similar to that previously described with respect to the letter "O," wherein logic circuits are utilized to turn on and turn off the electron gun during selected horizontal increments of the horizontal traces as they pass through the character slot in which a designated character is being formed. In comparing FIGS. 4A and 4B it should be noted that segments b through e, i.e., the upper and lower curved portions, are the same in both figures and, likewise, the electrical signals for horizontal traces Y.sub.1 -Y.sub.4 and Y.sub.13 -Y.sub.16 are the same in FIGS. 5A and 5B. Thus, these portions can be formed using the same logic circuits.

The display and electrical signals corresponding to the horizontal traces Y.sub.5 -Y.sub.12 differ for the letters "O" and "C" in that only the left hand vertical portion is formed in the letter "C." Since the signals on horizontal traces Y.sub.5 -Y.sub.12 differ, the same logic circuits can not be used, but due to the partial similarity, a portion of the logic circuits can, nevertheless, be common. This will be described more fully in connection with FIG. 7.

FIGS. 4C and 5C illustrate the display for the letter "G" and the corresponding electrical signals, respectively. In this illustration the letter "G" is not formed by simply combining separate portions which when combined make up the desired letter, but instead the logic circuits, in effect, form a complete letter "O," then remove a portion of the letter and thereafter add additional segments as required to complete the letter "G" configuration. As shown in FIG. 4C the segments a-f make up the letter "O" and are the same as those shown in FIG. 4A. The logic circuits are designed to disable character generation during increments X.sub.20 -X.sub.24 and, therefore, the portions of segments d, e, f and a shown in dotted lines in FIG. 4C do not appear as part of the visible display. In this manner a portion of the letter "O" has, in effect, been removed. Segments i and j are formed by separate logic circuits and added to the display. As indicated by some of the double cross-hatching, there is an overlap between segments j and e, but electrically this has no effect on the display since the intensity of the electron beam passing through this area remains the same as in other areas where the display appears.

The illustrations set forth in FIGS. 4A-4C and FIGS. 5A-5C are intended only by way of illustration to set forth the basic techniques which can be employed to reduce the logic circuitry required in the formation of a complete set of alpha-numeric characters. There are innumerable ways in which the individual characters may be divided up according to common portions so that individual portions of characters can be added or subtracted and combined as desired. The specific circuit implementation for achieving those results is specifically described in FIG. 7.

CONTROL SYSTEM

The control system for achieving a display as shown in FIGS. 1 and 4 is shown in block diagram form in FIG. 6.

The timing for the entire system is controlled by a clock pulse source 20 operating at a frequency of 2.016 megahertz, this being the rate at which the segments of successive characters are produced during a horizontal trace. The output of clock 20 passes through a six stage binary counter 21 to reduce the frequency to 31.5 kilohertz and then passes through a binary stage 22 to produce a 15.75 kilohertz signal, the latter being used to control the horizontal sweep and related functions. The 31.5 kilohertz signal from counter 21 is supplied to a 10 stage binery counter 23 which, in turn, is coupled to logic circuits 24 and 25 which detect the 520th and 525th counts respectively. Since the 31.5 kilohertz signal has a frequency twice the frequency of the horizontal sweep, the 525th count corresponds exactly to 262.5 horizontal lines and provides the control signal for the vertical drive at the 60 hertz rate. The output signal from circuit 25 is used to reset counter 23 upon occurrence of the 525th count.

The 15.75 kilohertz signal from counter 22 is supplied to a horizontal drive circuit 27 which provides a drive pulse for triggering successive linear ramp signals by means of a horizontal sweep circuit 28 which, in turn, drives a horizontal deflection amplifier 29. The 60 hertz signal developed by logic circuit 25 is supplied to a vertical drive circuit 37 which provides the pulses for triggering a vertical sweep circuit 38. The output of the vertical sweep circuit is supplied to a vertical deflection amplifier 39 where it is combined with a diddle sweep signal.

The incoming data for the system is stored in a circulating memory 30 which consists of a delay line in series with an amplifier to form a closed circulating loop. Also included in the circulating memory is control logic for organizing the received data for proper location within the circulating memory and address logic for designating the various stored signal locations. The introduction of data into the memory, or the removal of data from the memory, is controlled by the 2.016 megahertz clock 20. The time delay within the circulating memory is sufficient to provide storage capacity for the characters of the entire display frame, each character being in a six bit code.

Registers 31-36 provide temporary storage for data while being used in character generation. Each register has a capability of storing six bit character designations for an entire 128 character text line. The Channel 1A register 31, for example, includes six parallel 128 stage registers. The circulating memory 30 is preferably arranged to provide serial transfer of data into the registers which can be achieved by organizing all the data for the text line with the most significant bits first and ending with all the least significant bits. During the transfer of data into register 31, the six individual 128 stage shift registers can be connected in series and the data from the circulating memory passed via AND gate 41 in serial fashion. When the register is loaded, the six bit designation of the first character of the text line appears on six parallel output lines from the channel 1A register, the parallel output of the register being indicated by the parallel line arrow. These outputs are coupled to character generation logic unit 70 via multiple AND gates 51 capable of gating each of the individual parallel outputs. Advance pulses are supplied to register 31 via AND circuit 61 from clock 20, such that each time an advance pulse is applied the six bits of the next character designation appear at the outputs which are coupled to the character generation logic. The registers are designed so that data can be recirculated within the register as many times as desired.

Registers 32 and 33 are similarly constructed and operate in a similar fashion. The registers receive data in serial fashion via AND gates 42, 43 and are coupled to the character generation logic 70 via multiple AND gates 52 and 53, respectively. Advance pulses are received via AND gate 61. Registers 31-33 make up the A channel registers and provide temporary storage for data of an entire text block. The B channel registers 34-36 are also similarly constructed and operate in a similar fashion. They receive data in serial form via AND circuits 44 and 46 and are coupled to the character generation logic via multiple AND circuits 54-56. Advance pulses are supplied from clock 20 at the 2.016 megahertz rate via AND circuit 62.

The A and B channel registers operate alternatively so that one set of registers can be used to control the character generation logic during formation of a text block, while the other set of registers is receiving data from circulating memory 30. This control over the operation of the A and B channel registers is achieved by means of flip-flop circuit 60. When the flip-flop circuit is in the "1" state, multiple AND circuits 51-53 are enabled thereby coupling the A channel registers to the character generation logic, and AND gate 61 is enabled to permit the advance pulses 20 to pass into registers 31-33. At the same time AND circuits 44-46 are enabled so that data can be transferred from the circulating memory into the B channel registers. On the other hand, when flip-flop circuit 60 is in the "0" state, advance pulses are supplied to the B channel registers via AND gate 62 and the B channel registers are coupled to the character generation logic via multiple AND circuits 54-56 whereas the circulating memory is coupled to the A channel registers via AND circuits 41-43.

The Y-odd and Y-even registers 80 and 81 are each 10 stage recirculating shift registers utilized to circulate a single bit which designates the successive horizontal lines of the odd and even fields respectively. During the formation of the even field, register 80 designates the 10 successive lines of a text line whereas during formation of the odd field the 10 successive lines of a text line are designated by shift register 81, thereby making up the total of 20 lines per text line. The 10 parallel outputs of register 80 are coupled to the character generation logic via multiple AND gates 85 whereas the 10 individual outputs of register 81 are similarly coupled to the character generation logic via multiple AND gates 86. Advance pulses are supplied to the advance inputs "A" of registers 80 and 81 from counter 22 via AND circuits 83 and 84 respectively. Flip-flop circuit 82 receives a signal from count logic 25 which is applied to the binary input of the flip-flop circuit so that the flip-flop changes state in synchronism with the beginning of each successive field. The flip-flop circuit is in the "1" state during formation of the odd field and therefore AND circuit 83 is enabled to apply the advance pulses to register 80, and multiple AND gates 85 are also enabled thereby coupling the output of register 80 to the character generation logic. Flip-flop circuit 82 is in the "0" state during formation of the even field and in this state flip-flop circuit 82 enables AND circuit 84 so that advance pulses are supplied from counter 22 to register 81 via AND circuit 84, and the flip-flop circuit also enables multiple AND gates 86 to couple the output of register 81 to the character generation logic.

Pulses are supplied to the reset inputs "R" of registers 80 and 81 to insure that the registers begin the stepping sequence on the initial line during the formation of the first text block. For the odd field register 80 should commence the counting sequence on line 1 (as designated in FIG. 8) which coincides with commencement of the vertical sweep. Accordingly, the reset pulse for register 80 is derived from count logic circuit 25 which produces the pulse which triggers the vertical sweep. Thereafter, the register advances in repetitive 10 step sequences during the formation of 26 successive text blocks, i.e., lines 1-260 of the scanning pattern.

For the even field the counting sequence of register 81 should commence after a one-half line delay following commencement of the vertical sweep, i.e., at the beginning of line 264 as designated in FIG. 8. The half line delay is provided by flip-flop circuit 90 and associated AND gate 91. The signal developed by count logic circuit 25 signifies commencement of a vertical sweep at the beginning of the even field, and this signal is applied to the "set" input of flip-flop circuit 90 to place the flip-flop circuit in the "1" state. Flip-flop circuit 90 is connected to condition AND circuit 91 when in the "1" state. Upon commencement of the next horizontal trace which coincides with commencement of line 264, the pulse developed by counter 22 passes through conditioned AND gate 91 to reset register 81. The same pulse is also applied to the "reset" input of flip-flop circuit 90 to return the flip-flop circuit to the "0" state. Accordingly, register 81 commences its counting sequence on line 264 and thereafter repeatedly counts in a 10 step sequence during formation of the 26 text blocks of the even field.

When the circulating bit in either the Y-odd or Y-even registers 80 or 81 returns to the first stage of the register a pulse is developed by means of OR circuit 87 signifying that the lines forming a text block have been completed and the formation of a new text block is about to commence. The output of OR circuit 87 is coupled to the binery input of flip-flop circuit 60 to change the state of the flip-flop circuit so that a different one of the A or B channel registers is coupled to the character generation logic for formation of the next text block. The output of OR circuit 87 is also supplied to circulating memory 30 to initiate transfer of a new set of data into that one of the A or B channel registers not then connected to the character generation logic. In addition, the output of OR circuit 87 is coupled to diddle drive circuit 88 which develops a pulse for triggering a new diddle sweep via circuit 89 so that the diddle sweeps are in exact synchronism with the formation of the successive text blocks. The diddle sweep circuit 89 provides the linear ramp signal as shown in FIG. 3B and the output of the sweep circuit is supplied to amplifier 39 where it is combined with the vertical sweep signal developed by circuit 38. The signal at the output of amplifier 39 is supplied to the vertical deflection coils and corresponds to the signal shown in FIG. 3C.

The character generation logic and associated channel gates 71-73 and delay line 74 are described more fully hereinafter in connection with FIG. 7. Basically, the character generation logic receives signals from either the A channel registers 31-33 or the B channel registers 34-36 designating the character (in xix bit code) then being formed, and at the same time the character generation logic receives a signal from either register 80 or 81 indicating the particular line of the text block then being formed. In response to these inputs the character generation logic energizes selective ones of 24 output lines per channel according to the on-off control desired for a particular electron gun. If, for example, electron gun A is to form line Y.sub.1 of the letter "O" (see FIGS. 4 and 5) either register 31 or 34 would designate the letter "O" in six bit code and the Y-odd register energize its first output corresponding to line Y.sub.1. The twenty four output lines from character generation logic 70 which are coupled to channel one gates 71 are designated X.sub.1 -X.sub.24 (corresponding to the X.sub.1 -X.sub.24 designations in FIGS. 4 and 5) of which lines X.sub.8 -X.sub.17 would be energized for line Y.sub.1 in the formation of the letter "O." The channel one gates include 24 individual AND gates connected respectively to successive ones of lines X.sub.1 -X.sub.24 and to 24 successive outputs of a 24 stage delay line 74. The output of the 2.016 megahertz clock 20 is coupled to delay line 74 and the delay line provides 24 successively delayed pulses in the 50 nanosecond interval between successive clock pulses. The successively delayed pulses provided by delay line 74 pass through the AND gates corresponding to energized lines X8-X17 to thereby enable electron gun A to provide the character segment a as shown in FIG. 4. The output of the channel one gates is supplied to an amplifier 75 which, in turn, is coupled to the grid of electron gun A. Registers 32 and 35 in similar fashion operate in combination with the channel two gates 72 and amplifier 76, and registers 33 and 36 operate in conjunction with the channel three gates 73 and amplifier 77.

Since some of the horizontal traces cannot be used in the character generation, namely lines 261-263 and 524-525, it is desirable to provide blanking circuitry since the remainder of the control circuitry is in continuous operation and otherwise would provide meaningless displays on these lines. The completion of line 260 and line 523 occurs when count logic 24 provides a pulse, and the output of logic circuit 24 is therefore connected to the "set" input of flip-flop circuit 92. When flip-flop circuit 92 is in the "1" state it activates a blanking circuit 78 which, in turn, is coupled to disable amplifiers 75-77. Flip-flop circuit 92 is returned to the "0" state upon commencement of the first line at the top of either the odd or even field. For the odd field this occurs when flip-flop circuit 82 changes to the "1" state, and for the even field this occurs when AND circuit 91 produces a pulse. Therefore, these signals are applied to the "reset" input of flip-flop circuit 92 via an OR circuit 93.

CHARACTER GENERATION CIRCUITRY

The character generation circuitry for the system disclosed in FIG. 6 is shown in more detail in FIG. 7. For simplicity, only a portion of the complete character generation logic is shown, namely that portion used in the formation of the letters "O," "C" and "G" corresponding to the illustrations in FIGS. 4A-4C and 5A-5C. However, it is to be understood that a complete set of alpha-numerical characters can be developed according to the concepts illustrated in FIG. 7. Also, for simplification, only the logic for one channel is illustrated. AND gates 101-106 and 110, and OR circuit 111 correspond for example, to the channel one gates 71 in FIG. 6, and would be duplicated for other channels.

Delay line 74 can be of any suitable design capable of being triggered at a 2.016 megahertz rate and of dividing the approximately 50 nanosecond interval between triggering pulses into 24 successively delayed pulses without significant deterioration of pulse width or amplitude. A suitable delay line is disclosed in co-pending application, Ser. No. 806,472, filed on even date herewith, and incorporated herein by reference. The delay line disclosed in the corresponding application includes a series of inverting amplifier stages in cascade, the pulse passing down the amplifier chain being delayed by the successive turn-on time delays of each successive stage. The amplifier stages are connected to associated AND gates such as AND gates 101-106 and 110 in FIG. 7 so that the leading edge of the pulse passing down the amplifier chain controls both the enabling and disabling of the AND gates. As a result, the pulse width of the pulse passing down the amplifier chain may vary, but since the leading edge of the pulse controls both the enabling and disabling of the associated AND gates, the combination provides delayed pulses wherein the pulse width does not vary. With this circuit arrangement each of the AND gates 101-106 and 110 has two inputs derived from delay line 74 and a third input which is one of the lines X.sub.1 -X.sub.24 from the character generation logic. In addition some of the gates, such as gate 110 in FIG. 7 may include an inhibit input.

When a pulse from the 2.016 megahertz clock is applied to delay line 74, the pulse ripples through the successive amplifier stages enabling and disabling the gates 101-110 in succession. Successively delayed output pulses are developed by those of AND gates 101-110 which also receive an energizing signal from the associated line X.sub.1 -X.sub.24. The outputs from AND circuits 101-110 are coupled to separate inputs of OR circuit 111 which, in turn, is coupled to one of the amplifiers 75-77 in FIG. 6.

AND gates 200, 201 and 202 receive coded character data and are connected to provide output signals when the letters "O," "C" and "G" are designated for display by the registers 31-36. The output of AND circuits 200 and 202 are coupled to an OR circuit 203, and the output of AND circuits 200, 201 and 203 are coupled to an OR circuit 204. When the designation for the letter "O" is detected by AND circuit 200, a signal passes via OR circuit 204 to enable AND circuits 152-155 to form the upper and lower curved segments b-e as shown in FIG. 4A, and a signal passes via OR circuit 203 to enable AND circuits 151 and 156 to form the vertical portions including segments a and f. When the designation for the letter "C" appears, AND circuit 201 produces a signal which passes through OR circuit 204 to enable AND gates 152-155 to form the upper and lower curved portions, and also produces a signal which enables AND circuits 157 and 158 to form the vertical position, i.e., segments g and h shown in FIG. 4B. When the letter "G" is designated, AND circuit 202 develops a signal which passes through OR circuits 203 and 204 to, in effect, form the letter "O," i.e., segments a-f shown in FIG. 4C, and which enables AND circuits 159 and 160 to form segments i and j shown in FIG. 4C. The output of AND circuit 202 also passes through an amplifier 171 to provide the signal which inhibits the display during increments X.sub.20 -X.sub.24.

The respective outputs of the Y-odd and Y-even registers 80 and 81 (FIG. 6) are connected to respective inputs of OR circuits 141-150 and line 159 as designated in FIG. 7. The 10 successive outputs of the Y-odd register are designated Y.sub.1, Y.sub.3, Y.sub.5, Y.sub.7, Y.sub.9, Y.sub.11, Y.sub.13, Y.sub.15, Y.sub.17, Y.sub.19, and the 10 successive outputs of the Y-even register 81 are Y.sub.2, Y.sub.4, Y.sub.6, Y.sub.8, Y.sub.10, Y.sub.12, Y.sub.14, Y.sub.16, Y.sub.18 and Y.sub.20. When AND gates 151-156 and 160 are enabled, OR circuits 141-146 and 150 are coupled to amplifiers 161-166 and 170 respectively, which, in turn, are connected to lines 181-186 and 190. When AND circuits 157 and 158 are enabled, the outputs of OR circuits 141 and 146 are coupled to lines 187 and 188, respectively via amplifier 167 and 168. Line 149 is coupled to line 189 via amplifier 169 when AND circuit 159 is enabled. The output of amplifier 171 is coupled to line 191.

Some of the AND gates connected to delay line 74 have been eliminated to simplify the illustration, only AND gates 101-106, and 110 coupled to the lines X.sub.1 -X.sub.6 and X.sub.24, respectively, being shown. It is to be understood that additional AND gates in the complete system between gates 106 and 110 would be similarly connected to lines designated X.sub.7 -X.sub.23. The connections of lines 181-190 to the various X lines are designated for each line toward the right in FIG. 7. Accordingly, line 181 is connected to lines X.sub.2, X.sub.3, X.sub.4, X.sub.5, X.sub.20, X.sub.21, X.sub.22 and X.sub.23 as designated. Of these connections only the connections to lines X.sub.2, X.sub.3, X.sub.4 and X.sub.5 via OR circuits 122-125, respectively, are specifically shown. In similar fashion lines 182-190 are connected to the X lines designated in FIG. 7 via the OR circuits 121-130. OR circuits 121-130 would also receive similar inputs from character generation logic for other characters.

Line 191 is connected to an inhibit input of AND circuit 110. AND circuit 110 is so constructed that when a signal is present on the inhibit input, it cannot produce an output signal regardless of what signals may be present on other inputs. The designation to the right on line 191 indicates that the gates corresponding to increments X.sub.1 -X.sub.24 are to be inhibited when line 191 is energized and, hence, the corresponding gates are constructed similar to gate 110.

In operation, if the letter "O" is designated and AND gates 151-156 are enabled, the letter "O" would be generated on the display screen. When line Y.sub.1 is energized producing an output from OR circuit 142, indicating that the first horizontal trace of a text line is being formed, a signal is developed which passes through AND gate 152 and amplifier 162 to energize line 172. Line 172 is, in turn, coupled to lines X.sub.8 -X.sub.16 to enable the associated AND circuits coupled to delay lines 74. During the first seven pulses which are applied to AND gates associated with non-energized lines X.sub.1 -X.sub.7, no output pulses would be produced. Thereafter, when the delay line enables the AND circuits associated with lines X.sub.8 -X.sub.16 energized from line 172, corresponding output signals are produced and these successive signals are combined in OR circuit 111 to provide a continuous energization signal during the corresponding interval. Thereafter, the delay line enables AND gates associated with lines X.sub.17 -X.sub.24, but these lines are not energized and, therefore, the corresponding output pulses are not produced. The result is the segment b shown in FIG. 4A.

Because of the interlace arrangement in the overall system, the next line which would be produced would be the third line Y.sub.3. When line Y.sub.3 is energized a signal is produced on the output of OR circuit 144 which, in turn, energizes line 174. Line 174 energizes lines X.sub.5 -X.sub.8 and X.sub.17 -X.sub.20 to provide output pulses at corresponding intervals to thereby develop segments d as shown in FIG. 4. Thereafter, the remaining odd lines of the text line are formed in succession. Subsequently, when the even field is being formed, the lines Y.sub.2, Y.sub.4, Y.sub.6, etc., will be energized in succession to thereby complete development of the letter "O" on the viewing screen.

If the letter "C" is designated, AND circuits 152-158 are enabled and the Y line designation signals applied to OR circuits 141-146 produce signals on line 182-185, 187 and 188 to form the letter "C." Note that because of the similarity in the left side vertical portions of the letters "O" and "C," the same OR circuits 141 and 146 are used in forming segments a and f in FIG. 4A and in forming segments g and h in FIG. 4B.

If the letter "G" is designated, AND circuits 151-156, 159 and 160 are enabled and the Y line designation signals applied to OR circuits 141-146, 150 and line 149 produce signals on lines 181-186, 189 and 190 which produce segments a-f, i and j. The signal developed in line 191 inhibits the gates corresponding to horizontal increments X.sub.20 -X.sub.24.

OPERATION OF THE SYSTEM

In order to describe the operation of the overall system, it is necessary to assume certain initial conditions since the system operates in continuous fashion. Assume that flip-flop circuit 60 is in the "1" state, and that the A registers 31-33 are loaded with data for the formation of the first text block. Flip-flop circuit 82 is assumed to be in the "1" state indicating that the odd field is going to be formed and that, therefore, the Y-odd register 80 is active. The Y-odd register is assumed to be in its reset state with the Y.sub.1 output thereof being energized. Flip-flop circuits 90 and 92 are both in the "0" state. Upon commencement, the horizontal, vertical, and diddle sweeps start simultaneously.

These assumed conditions correspond to the beginning of the scanning pattern for a display frame on the screen.

As the electron beams of the three guns move horizontally forming the first set of horizontal traces, the A channel registers 31-33 receive advance pulses from clock 20 advancing the data in these registers so that the 128 character designations of the text line appear at the output of the registers in sequence. For each character designation a pulse is supplied to delay line 74 which, in turn, develops pulses through channel gates 71-73 to turn on and turn off electron guns A, B and C for appropriate increments during the formation of each successive character. This control is achieved by means of the character generation logic which has activated selective ones of the gates in channel gate circuits 71-73 according to the character designations provided by registers 31-33. The first set of horizontal traces are completed in 64 microseconds at which time the upper segments of all characters in the first three text lines (first text block) have been formed on the screen.

Upon completion of the first set of horizontal traces, the A channel registers 31-33 have recirculated the data and the data has therefore returned to its initial position with the first character designations of the text lines appearing at the outputs of the registers. Accordingly, the data in the A channel registers is ready for commencement of a second set of horizontal traces. At this time counter 22 provides a pulse which is supplied to horizontal drive circuit 27 to trigger a new horizontal sweep. The same pulse is also applied to register 80 via AND circuit 83 to advance the register to the next horizontal line designation. Since the entire scanning pattern consists of two interlaced fields, the next horizontal line designation provided by register 80 is line Y.sub.3. The second set of horizontal traces corresponding to line Y.sub.3 of the first text block is then formed according to the successive character designations under control of A channel registers 31-33 as further broken into successive horizontal increments by means of delay line 74, character generation logic 70 and the channel gate circuits 71-73.

Thereafter, the remaining eight sets of odd lines of the first text block are completed in succession. Upon completion of the text block, counter 22 again provides a pulse which triggers a new horizontal sweep and advances register 80. Register 80, which has previously reached a full count, resets in response to this pulse and provides an output pulse via OR circuit 87. This output pulse is applied to diddle drive circuit 88 to trigger a new diddle sweep which drops the three beams into a lower position for formation of the second text block. The pulse from OR circuit 87 also shifts flip-flop circuit 60 to the "0" state so that the B registers 34-36 are coupled to the character generation logic 70. These B registers have previously been loaded with data from circulating memory 30 for formation of the second text block. The pulse from OR circuit 87 also goes to circulating memory 30 to initiate the transfer of data for the third text block into A registers 31-33. The system then proceeds to form the second text block and thereafter continues in similar fashion to form the remainder of 26 text blocks of the odd field.

During formation of the 26th text block, data for the first text block is loaded into the A channel registers 31-33. After completion of the 26th text block, the system attempts to continue with the formation of a 27th text block using the data supplied for the first text block. However, upon completion of the 26th text block, count logic circuit 24 produces a pulse which places flip-flop circuit 92 in the "1" state to disable amplifiers 75-77 via blanking circuit 78. Therefore, the abortive attempt of the system to produce a 27th text block is of no effect.

Shortly thereafter, count logic circuit 25 provides a pulse signifying the completion of 262.5 lines of the scanning pattern, this being the end of the odd field. The pulse from logic circuit 25 is supplied to vertical drive circuit 37 to trigger a new vertical sweep and to flip-flop circuit 90 to place this circuit in the "1" state. The next pulse provided by counter 22 occurs upon commencement of line 264 which is the uppermost complete line of the even field. The pulse from counter 22 triggers a new horizontal sweep via circuits 27-29, passes through AND circuit 91 to reset register 81, and passes through OR circuit 93 to reset flip-flop circuit 92 to again enable amplifiers 75-77. When register 81 is reset, its output designates line Y.sub.2 which is the uppermost line of the first text block in the even field.

Since text data for the first text block has previously been loaded into the A channel registers 31-33, the system proceeds to form the even lines of the first text block under control of Y-even register 81. These lines interlace with the previously formed odd lines to thereby complete the 20 lines of the first text group. Thereafter, successive odd lines of successive text groups are formed and upon completion of the 26th text group, logic circuit 24 produces a pulse which again disables amplifiers 75-77.

Upon completion of 262.5 lines of the even field, logic circuit 25 again produces a pulse which signifies both the end of the even field and the end of a frame consisting of 525 complete lines. This pulse from logic circuit 25 is applied to the vertical drive circuit 37 to trigger a new vertical sweep and is also applied to reset register 80. The same pulse returns flip-flop circuit 82 to the "1" state which, in turn, resets flip-flop circuit 92 via OR circuit 93. Data for the first text block has previously been loaded into A registers 31-33. Thus, the sequence is complete and has returned to the starting point and, therefore, the system automatically commences producing another frame.

Although only one illustrative embodiment has been described in detail in the foregoing specification, it should be obvious that there are numerous variations in the circuit configurations and operating sequences which are within the scope of the contemplated invention. The invention is more particularly defined in the appended claims.

Claims

1. Apparatus for providing an alpha-numeric display comprising a cathode ray tube including at least one electron beam adapted to scan the viewing surface of said cathode ray tube in successive horizontal traces to provide an alpha-numeric display frame, the individual alpha-numeric displays appearing in successive character slots of a text line including a plurality of horizontal traces; circuit means for providing a plurality of successively delayed pulses synchronized with the passage of said electron beam through each character slot; character designating means operative in synchronism with the movement of said electron beam to designate the character to be displayed in each character slot including; a series circulating memory for storing incoming coded character data for the entire alpha-numeric display frame at serial time positions according to the display position of the individual characters on said cathode ray tube, a temporary recirculating register operatively connected to receive series coded data groups for complete text lines from said circulating memory, and circuit means for controlling the transfer of coded data for a complete text line to said recirculating register just prior to formation of the text line on said cathode ray tube and for advancing the data in said recirculating register character-by-character in synchronism with the movement of said horizontal traces through successive character slots of each horizontal trace and through successive horizontal traces of a text line; logic circuit means coupled to said character designating means for designating for display selected horizontal increments of the horizontal trace passing through a character slot according to the character designation for the character slot, each horizontal increment corresponding in time to one of said delayed pulses; and gate circuit means coupled to said circuit means for providing delayed pulses and to said logic circuit means to pass delayed pulses corresponding in time those of said horizontal increments designated for display, said gate circuit means being connected to said cathode ray tube

2. Apparatus according to claim 1 wherein said circuit means for providing

3. Apparatus according to claim 2 further comprising a source of clock pulses coupled to said register and said delay line to advance said register and to trigger said delay line in synchronism with the passage of

4. Apparatus for providing an alpha-numeric display comprising a cathode ray tube including at least one electron beam adapted to scan the viewing surface of said cathode ray tube in successive horizontal traces to provide the alpha-numeric display, the alpha-numeric characters appearing in successive character slots of a text line; a delay line for providing a plurality of successively delayed pulses when triggered, said delayed pulses being synchronized with the passage of said electron beam through each character slot; a circulating register for storing coded data designating the characters to be displayed in the character slots of a text line, said register being advanced to designate a different character each time an advance pulse is applied thereto and to recirculate said data for use during successive horizontal traces of a text line; said circulating register including a number of parallel shift registers equal to the number of bits in said code for designating characters, each of said shift registers having a number of stages equal to the number of characters in a text line and being connected to recirculate data, and said shift registers being connected to shift data in synchronism; a clock pulse source coupled to said delay line to supply triggering pulses thereto, and coupled to said circulating register to supply advance pulses thereto; logic circuit means coupled to said circulating register for designating, for display, selected horizontal increments of the horizontal trace passing through a character slot according to the character designation for the character slot, each horizontal increment corresponding in time to one of said delayed pulses; and gate circuit means coupled to said delay line and to said logic circuit means to pass delayed pulses corresponding in time those of said horizontal increments designated for display, said gate circuit means being connected to said cathode ray tube to control the intensity of said

5. Apparatus according to claim 4 further including means for individually designating the horizontal traces of a text line, said logic circuit means being connected to said last named means and operative to designate, for display, horizontal increments selected according to the designations of

6. Apparatus according to claim 4 further comprising counter means connected to said clock pulse source, said counter means being operatively connected to trigger a new horizontal trace of said electron beam each time a predetermined number of pulses have been received from said clock

7. Apparatus according to claim 6 further comprising means for individually designating the horizontal traces of a text line, said last named means being so connected to said counter means that a different horizontal trace is designated each time said predetermined number of pulses is received, said logic circuit means being connected to said last named means and operative to designate, for display, horizontal increments selected

8. Apparatus according to claim 6 further comprising second counter means coupled to said clock pulse source, said second counter means being operatively connected to trigger a new vertical deflection sweep of said electron beam each time a predetermined number of pulses have been received from said clock pulse source.