Digital Correlator And Integrator

Abstract

A digital correlator and integrator which uses a core memory to implement the cross-correlation and post-integration operations simultaneously. The system is a hybrid correlator that treats one of two sample channels linearly while it delays and stores the information in the other channel. The samples from both channels are multiplied together then averaged repetitively into stored data to generate a time-compressed correlation function which is retained in digital form within the memory.

Description

BACKGROUND OF THE INVENTION

This invention generally relates to the art of signal correlation and in particular to an apparatus for developing a time-compressed correlation function of two signals.

Correlation function analysis has long been used to calculate the most probable value of delay between information bearing signals which are transmitted over noisy communication channels. Numerous devices have been proposed in the past for carrying out this type of correlation function analysis, such as the hybrid correlator disclosed in U.S. Pat. No. 3,373,359 to C. N. Pryor, Jr. et al. issued Mar. 12, 1968. The device described therein is known as a hybrid correlator because it treats one input channel linearly while the other channel is time-compressed and polarity quantized. This type of correlator possesses the disadvantage of having an extremely short integration time which may be, for example, only a single sample period. In addition, correlators of the type disclosed in the Pryor, et al. patent are relatively complicated because they use a delay line time compressor which may be of the type disclosed in U.S. Pat. No. 2,958,039 issued to Victor C. Anderson on Oct. 25, 1960. Such time compressors are relatively expensive and delicate, requiring the use of quartz delay lines, band pass filters, and other costly components.

SUMMARY OF THE INVENTION

Accordingly, one object of this invention is to provide an improved correlator that is both rugged and inexpensive.

Another object of this invention is to provide an improved hybrid digital correlator and integrator having an adjustable integration time.

Yet another object of this invention is to provide an improved hybrid digital correlator and integrator for accomplishing cross correlation and post integration functions simultaneously.

Briefly, these and other objects are achieved by sampling each of two inputs periodically, multiplying the two samples together, and averaging the produce with a word brought from a memory bank. This process is repeated for each word stored in memory between sampling times, while the sample of one channel is cyclically replaced by values of input from that channel stored in memory, until the entire correlation function in time compressed form has been updated.

BRIEF DESCRIPTION OF THE DRAWING

A more complete description appreciated of the invention and many of the attendant advantages thereof the attendant advantages thereof will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawing wherein:

the sole FIGURE is a schematic block diagram of the digital correlator and integrator of the instant invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the sole FIGURE, the instant invention is shown as including a pair of input terminals 10 and 12 coupled to a pair of sample gates 14 and 16, respectively. Terminals 10 and 12 are connectable to any suitable sources of input signals F.sub.1 and F.sub.2 such, for example, as the outputs of submerged hydrophones. It will be noted that F.sub.1 and F.sub.2 may be either independent signals, or they may be elements of the same generic signal sensed at different positions or at different times, as by separated transducers.

A digital clock 18 is coupled through a frequency divider 20 to both of gates 14 and 16 to permit sampling at selected periodic intervals. Divider 20 ensures that the sampling frequency is less then the maximum frequency of clock 18 thereby permitting time compression of the generated correlation function, as is more fully described hereinafter. Sample gate 14 is coupled to an analog to digital converter 22 which digitizes the amplitude of the sample of signal F.sub.1. Sample gate 16 is coupled to a clipper 24 which hard clips, or polarity quantizes the sample of signal F.sub.2 thereby retaining only the changing polarity information at that signal. Clipper 24 is coupled to a temporary storage unit 26 which stores the polarity quantized sample information. Temporary storage unit 26 may be an ordinary flip-flop or any equivalent bistable storage unit. Both analog to digital converter 22 and temporary storage unit 26 are coupled to a multiplier 28 in which the product of the F.sub.1 sample and the polarity quantized output of the F.sub.2 sample is developed. The output of multiplier 28 is coupled to a substractor 30, whose output in turn is coupled to the input of a divider 32, whose output in turn is coupled to an adder 34, whose output in turn is coupled to the input of a primary memory 36, the functions of which circuit stages will be explained more fully hereinafter.

Primary memory 36, which may be a conventional unit of either random or serial access, is coupled at its output to a buffer 38 as well as to subtractor 30 and adder 34. The primary memory inputs are coupled to both temporary storage unit 26 and adder 34. Digital clock 18 is directly coupled to memory 36 to control its read and write cycles in the conventional manner. The body or storage section of memory 36 is divided into a first storage section 40 and a second storage section 42, the first section storing numerous multibit words while the second section stores only single bits of information. It will be understood that the memory need not be physically divided into two sections, but the inputs and outputs need only be handled so as to segregate one bit from each complete stored word. This is necessary in order that the multiple bit correlation function points which have been stored in section 40 can be stored and handles separately from the single bit samples of F.sub.2 stored in section 42.

When a memory read cycle is initiated by a pulse from clock 18, the first stored correlation function calculation word is read from memory 36 into subtractor 30 and adder 36, while the first stored F.sub.2 sample is read into buffer 38.

In subtractor 30, an error signal is developed consisting of the difference between the F.sub.1 F.sub.2 sample product formed in multiplier 28, and the correlation function calculation word transferred from memory 36. This error signal is then digitally divided in divider 32 which has an preferably adjustable division factor .alpha. greater than unity to provide for variations in the integration time of the system. It will be understood that, in general, increasing the integration time improves the accuracy of the correlation function generated by the system and that the maximum integration time attainable is limited by the maximum word length storable in primary memory 36.

The relationship between the division operation and integration time may not be immediately apparent. To facilitate understanding of this relationship, it should be recognized that the error signal computed in subtractor 30 is divided in divider 32, and the quotient is subsequently used as a correction factor to be added to values previously stored in memory 36. If the division factor .alpha. i.e., approaching unity, is small, the correction factor is large thereby causing large changes in the stored data, If, in turn, the division factor .alpha. is much greater than unity, the correction factor is small thereby causing correspondingly smaller changes in the stored data. Thus, a large division factor .alpha. is analogous to a long integration time since it causes small incremental changes in the stored values of the correlation function, thereby requiring a longer time interval before the stored values of the correlation function respond to changing input samples. In turn, if the division factor .alpha. is made small, approaching unity, the correction factor has a larger effect on the stored values of the correlation function, analogous to a short integration time. The choice of an appropriate integration factor depends upon numerous practical considerations such, for example, as the size selected for primary memory 36, the accuracy of the desired result, and the maximum number of recirculations or corrections desirable before the output is to be read out.

The output of the signal developed in divider 32 is passed to adder 34 which is connected at both its input and output to primary memory 36. In adder 36 the correction factor developed in divider 32 is added to the word initially drawn from memory to form a new or updated value of the correlation function, which is then written into memory 36.

The same write cycle that causes the corrected value in adder 34 to be written into memory 36 also causes the value stored in buffer 38 to be transferred to temporary storage unit 26, and the value previously stored there to be written into section 42 of memory 36. The new value of F.sub.2 that has been drawn from memory 36 through buffer 38 is then multiplied with the original F.sub.1 sample retained in multiplier 28. Another word is read from memory and the subtraction, division and addition operations previously described are repeated, culminating in the calculation of another point on the correlation function. This cycle is repeated until all values of F.sub.2 stored in memory 36 have been scanned, and the entire correlation function has been updated.

The values of the correlation function may be read out to any suitable type of a utilization device or apparatus 44. For example utilization device or apparatus 44. For example utilization apparatus 44 may consist of a digital to analog converter coupled to an oscilloscope. In this case reading out the contents of primary memory 36 creates a conventional display of a correlation function with a peak at the most probable value of delay between the input signals. The utilization may also be various other signal processing logic which requires a correlation function input.

It will be noted that the number of words storable in memory 36 is preferably the same as the division factor of divider 20, so that the system scans through every stored value in the memory between openings of sample gates 14 and 16. This results in the correlation function stored in primary memory 36 being time compressed.

The invention may be extended to a true multiplier correlator to improve the accuracy of the calculated correlation function by replacing clipper 2 with an analog digital converter similar to 22. If this is done, all the remaining elements of the system must be expanded to handle the additional data that is utilized. For example, temporary storage unit 26 must be expanded from a flip-flop store to a multiple bit storage unit. In addition multiplier 28, subtractor 30, divider 32, adder 34, primary memory 36 and buffer 38 must all be expanded to operate on the increased amount of data.

Obviously, numerous additional modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described herein.

Claims

What is claimed as new and desired to be secured by Letters Patent of the United States is:

1. A digital correlator and integrator comprising:

first sampling means for sampling a first input analog signal;

second sampling means for sampling a second input analog signal;

an analog-to-digital converter coupled to the output of said first sampling means for converting the sampled first input analog signal into a first digital signal;

means for polarity quantizing the sampled second input analog signal to thereby produce a second digital signal;

temporary storage means for temporarily storing said second digital signal and for thereafter temporarily storing previously generated second digital signals;

multiplying means for digitally multiplying said first digital signal with said second digital signal to form a digital product signal representative of the instantaneous estimate of a point of a correlation function;

memory means having a first storage section for storing a plurality of previously calculated estimates of points of said correlation function, and a second storage section coupled to the output of said temporary storage means for storing said second digital signal and said previously generated second digital signals;

subtraction means coupled to the output of said multiplying means and coupled to the output of said first storage section for digitally subtracting a selected one of said previously calculated estimates of said points of said correlation function from said digital product signal;

division means coupled to the output of said subtraction means for dividing the output of said subtraction means by a predetermined scale factor; and

addition means coupled to the output of said division means and coupled to the input of said first storage section for adding said selected one of said previously calculated estimates of said points of said correlation function to the output of said division means to produce an updated estimate of said point of said correlation function.

2. The digital correlator and integrator of claim 1, wherein said first sampling means comprises a sample gate and said second sampling means comprises a sample gate.

3. The digital correlator and integrator of claim 1, wherein said means for polarity quantizing said second input analog signal comprises a hard clipper.

4. The digital correlator and integrator of claim 1, further including a buffer coupled between the output of said second storage section and the input to said temporary storage means for temporarily storing said previously generated second digital signals.