Transition Code Recognition System

Abstract

An electronic identification system for obtaining information from data-encoded labels in which a plurality of contiguous colored bars are printed on the data-encoded labels, each colored bar being of a color different from the color of its neighboring colored bars, is disclosed. The data-encoded label is scanned by a probe which images a spot of light on the label and which receives, from the label, reflected light signals that are supplied to the identification system. The identification system is constructed to receive and to decode a predetermined number of data bits according to a "size code" that is contained on the label, to perform a parity check of the data bits that are encoded on the label, and to transmit the decoded data to a data utilization device regardless of whether the probe traversed the label in a forward direction or in a reverse direction.

Description

BACKGROUND OF THE INVENTION

Light-reflective data-encoded labels have been employed to advantage in a number of applications. For example, data-encoded labels have been attached to articles that are sold in department stores and in food markets, and identification systems have been employed to read the labels and to transmit the decoded data to a data utilization device which used the date for inventory control purposes. Data-encoded labels have also been attached to various vehicles--for example, railroad cars--which pass a sensing station, wherein the data-encoded label contained information concerning the vehicles' origin and destination and the type of freight being carried by them.

Some of these prior label identifications systems have employed a light beam to scan the label at a fixed scanning rate, and some of them have required accurate registration between the label and the scanning probe. The disadvantages of these prior identification systems are that they are complex and costly or are inconvenient to use, and they are, therefore, impractical when a large number of scanning probes must be employed, as, for example, in a department store or in a food market where each checkout clerk must have his own scanning probe.

A disadvantage of prior data-encoded labels which are read when the label and the sensing device, such as a hand-held probe, are in motion relative to one another is that the size of the label is too large for many applications. A clock-colored bar must be provided for each data-colored bar of the label that is employed in this type of system, and, therefore, twice as many colored bars as are necessary to display the data alone are required. When clock-colored bars must be provided in addition to data-colored bars, or when a complex encoding configuration must be established on the label for alignment purposes, the cost of printing the labels may become excessive, since thousands of labels may be employed in a single food market or in a single department store.

The data-encoded labels that are decoded by the identification system of the disclosed invention have no clock colored bars, and, therefore, the size of these labels is approximately one-half the size of prior data-encoded labels which contained the same information but which included clock colored bars. The use of the data-encoded labels that are sensed and decoded by the identification system of the disclosed invention is, therefore, feasible in many situations where the use of the prior data-encoded labels would not be feasible, and the reduction of label size that is achieved by these labels is important, since a reduction in label size beyond a certain point through improved probe design alone is impractical. In addition, the identification system of the disclosed invention decodes information that is derived from these data-encoded labels regardless of whether the sensing probe has traversed the sensed labels in a forward direction or in a reverse direction, and it also checks the parity of the data that is decoded from the sensed labels even though the labels that are sensed may contain a substantially different number of data bits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a data-encoded label.

FIG. 2 shows sectional views of the scanning probe, the light source, and the dichroic mirror section, and an overall block diagram of the identification system and data utilization device.

FIG. 3 is a sectional view of a bundle of fiber optic filaments that are shown in FIG. 2 taken along the line 3--3 of FIG. 2.

FIG. 4 is a block diagram of the identification system.

FIG. 5A is a first portion of the schematic of the video processing section.

FIG. 5B is a second portion of the schematic of the video processing section.

FIG. 5C is a third portion of the schematic of the video processing section.

FIG. 6A is a first portion of the block diagram of the decoding section.

FIG. 6B is a second portion of the block diagram of the decoding section.

FIG. 7 is a block diagram of the input register section.

FIG. 8 is a block diagram of the end-of-label detection section.

FIG. 9 is a block diagram of a first part of the memory input synchronization section.

FIG. 10 is a block diagram of a second part of the memory input synchronization section.

FIG. 11 is a block diagram of the memory section.

FIG. 12 is a block diagram of the comparison section.

FIG. 13 is a block diagram of the program counter section.

FIG. 14 is a block diagram of the parity check section.

FIG. 15A is a first portion of the block diagram of the output register section.

FIG. 15B is a second portion of the block diagram of the output register section.

FIG. 16 is a block diagram of a first part of the control section.

FIG. 17 is a block diagram of a second part of the control section.

FIG. 18 is a timing diagram of various decoding signals.

FIG. 19 is a block diagram of a portion of the identification system which illustrates the synchronization of data flow into the memory section.

TECHNICAL DESCRIPTION OF THE INVENTION

The data-encoded label that is shown in FIG. 1 consists of a plurality of contiguous colored bars, each colored bar being one color of three or more colors and of a color different from the color of its neighboring colored bars. The colors that are employed in the label of FIG. 1 are green, black, and white. The green and black colored bars are printed over a white background, so that the white colored bars are defined by areas where no green or black colored bars are printed. The label employed in the disclosed invention is encoded so that it may be read by a sensing probe which travels over the label either in a forward direction or in a reverse direction. In addition, the label contains a "size code" which enables the identification system to decode labels which have a substantially different number of data digits, where a data digit consists of four data bits and each data bit is represented by a transition from one colored bar to another colored bar. Data-encoded labels that may be read by the identification system of the instant invention are described in more detail in the concurrently filed U.S. Pat. application of John B. Christie entitled "Transition Code Recognition System," which also is assigned to the assignee of the present application.

If it is assumed that a scanning probe traverses the label 20 in a left-to-right direction, the first color transition of the label 20 that is sensed by the probe will be the transition from the white background color to the green colored bar 22 and this transition represents a first "direction" bit. The next four color transitions are associated with the colored bars 24, 26, 28, and 30, and they are green-to-black, black-to-green, green-to-black, and black-to-green transitions, respectively, which represent the "size code" bits that specify the number of data bits that are contained on the encoded label 20. The transition from the colored bar 22 to the colored bar 24 represents a "size code" bit that has a code weight of 16, whereas the transition from the colored bar 28 to the colored bar 30 represents a "size code" bit that has a code weight of 2. Thus, the code weights of the "size code" bits that are associated with the colored bars 24, 26, 28, and 30 decrease as the probe traverses the label 20 in a left-to-right direction.

The first color transition that is sensed by the scanning probe after the "size code" transitions have been sensed is a first parity transition from the colored bar 30 to the colored bar 32, which in the illustrated label 20 is a green-to-black color transition. The next four color transitions that are sensed as the probe travels in a left-to-right direction are associated with the colored bars 34, 36, 38, and 40, which represent the four bits of the highest-order digit of the encoded data. The color transition from the colored bar 32 to the colored bar 34 is a black-to-green transition, and it has a code weight of 1; the color transition from the colored bar 38 to the colored bar 40 is a white-to-black color transition, and it has a code weight of 8; and, therefore, the code weights that are associated with the bits of the highest-order digit of the encoded data increase as the probe traverses the label 20 in a left-to-right direction.

The color transitions that are associated with the colored bars 42, 44, 46, and 48 represent the four bits of the lowest-order digit of the encoded data. The color transition from the colored bar 42 to the colored bar 44 is a black-to-white transition, and it has a code weight of 1. The color transition from the colored bar 48 to the colored bar 50 is a black-to-white transition, and it has a code weight of 8; and, therefore, the code weights of the lowest-order digit, like the code weights of the highest-order digit and also like the code weights of the other digits of the encoded data, increase as the probe traverses the label 20 in a left-to-right direction. The color transition from the colored bar 50 to the colored bar 52 is a white-to-black transition, and, like the color transition from the colored bar 30 to the colored bar 32, it represents a parity bit; however, signals which have opposite binary values will be decoded from these two transitions regardless of the direction of scan of the probe.

The color transitions associated with the colored bars 52, 54, 56, and 58 represent the four bits of the "size code," which are also represented by the color transitions associated with the colored bars 24, 26, 28, and 30. However, the code weight of the bit that is represented by the color transition from the colored bar 52 to the colored bar 54 is 2, and the code weight of the bit that is represented by the color transition from the colored bar 58 to the colored bar 60 is 16; therefore, the code weights of the "size code" bits that are associated with the colored bars 52, 54, 56, and 58 increase as the probe traverses the label 20 in a left-to-right direction. The color transition from the colored bar 58 to the colored bar 60 is a black-to-white transition, and it represents a second "direction" bit.

The data bits that are represented by the color transitions of the label 20 are shown below the label 20 in FIG. 1. The arrows on the left-hand side of FIG. 1 represent the scan direction of the probe. It is seen therefore, that, when the scanning probe traverses the label in a right-to-left direction, the bits which are decoded are transposed and inverted with respect to the data bits which are decoded when the probe traverses the label in a left-to-right direction. The manner in which data is encoded on the label is a function of the sequence in which the colored bars appear on the label 20. For example, if the probe travels across a white colored bar to a black colored bar, across a black colored bar to a green colored bar, or across a green colored bar to a white colored bar, a logic level "1" is decoded by the identification system in each instance. On the other hand, if the probe travels across a white colored bar to a green colored bar, across a green colored bar to a black colored bar, or across a black colored bar to a white colored bar, a logic level "0" is decoded by the identification system in each instance.

An example of a sensing probe that may be employed in the present invention is shown in FIG. 2, where the probe 62 is designed for use by a checkout counter clerk or by a department store employee or other operator. The sensing probe 62 is approximately the size of a pencil, and it is shaped like a pencil, so that it can be easily manipulated by the operator. Other types of sensing devices obviously may be employed in conjunction with the disclosed invention, and, in addition, it is not essential that the sensing device be in motion as long as there is relative motion between the data-encoded label and the sensing device.

The light source 64 that is mounted in the housing 68 may be a conventional tungsten filament light bulb. The conventional condensing lenses 70 and 72, which focus light from the light source 64 onto the fiber of the light-conducting filaments of the branch 78 of the bundle 74 of the fiber optic filaments, are also mounted in the housing 68. The condensing lens may be an integral part of the light source 64 if desired.

The branch 78 of the bifurcated bundle 74 of the fiber optic light-conducting filaments contains fiber optic filaments which are employed to conduct a light from the housing 68 to the probe 62 and onto the label 20. The branch 80 of the bundle 74 of fiber optic filaments contains fiber optic filaments which are used to direct the light that is reflected from the label 20 to the dichroic mirror section 76. The bundle 74 of fiber optic filaments has a conventional, abrasion-resistant coating that encloses the fiber optic filaments of the bundle 74. The probe ends of the fiber optic filaments of the bundle 74 are passed through the center of the plug 82, where they are secured to the plug 82.

FIG. 3 is a sectional view of the probe 62 taken along the like 3--3 of FIG. 2 and shows a portion of the probe 62, a first epoxy-adhesive layer 86, a portion of the plug 82, a second epoxy-adhesive layer 88, and the fiber optic light-conducting filaments 90. The fiber optic filaments 90 are conventional fiber optic light-conducting filaments, and, for example, they may be on the order of 0.003 inch in diameter. The light-colored circles representing the fiber optic filaments 90 in FIG. 3 represent the fiber optic filaments which are contained in the branch 78 of the bundle 74, and the dark-colored circles represent the fiber optic filaments which are contained in the branch 80 of the bundle 74.

The probe 62, which receives the light that is conducted down the branch 78 of the bundle 74 from the light source 64, has a conventional objective lens 94 mounted in it to direct a spot of light onto the label 20 that has a diameter that is approximately equal to the width of the colored bars of the label 20. The light that is reflected from the label 20 passes through the lens 94 to the fiber optic filaments of the branch 80 of the bundle 74, and these fiber optic filaments conduct the light to the dichroic mirror section 76.

The housing 98 of the dichroic mirror section 76 contains the dichroic mirror 100, or other signal-splitting device, and two light-responsive elements 102 and 104, which may be photodiodes or other light-responsive devices. The dichroic mirror 100 transmits the portion of the incident light which is in the infrared spectrum to the infrared-sensitive light-responsive element 104, and it reflects the remainder of the incident light to the noninfrared-light-responsive element 102. Both the infrared and the noninfrared light-signal components are reflected from the label 20 when the light spot from the probe 62 is imaged onto a white colored bar. When the light spot from the probe 62 is imaged onto a black colored bar, neither the infrared nor the noninfrared light-signal components are substantially reflected from the label 20. When the light spot from the probe 62 is imaged onto a green colored bar, the noninfrared light-signal component is absorbed, and the infrared light signal component is reflected. Although, in the described embodiment, the colored bars of the label 20 are green, black, and white colored bars, it is obvious that other suitable combinations of colored bars may be employed. When infrared and noninfrared light-signal components are employed by the identification system, a white colored bar may be replaced by a bar or any color that reflects both noninfra-red and infrared or near infrared. A green colored bar may be replaced by a bar of any color that absorbs noninfrared or red and either reflects or is transparent to infrared or near infrared, and a black colored bar may be replaced by a bar of any color that absorbs both the noninfrared and the infrared light-signal components.

Output signals from the light-responsive elements 102 and 104 are coupled through the amplifier section 106 of FIG. 2, which contains two amplifiers, each of which amplifies the output signal from one of the light-responsive elements 102 and 104. The amplified output signal from the light-responsive element 102 is coupled through the amplifier section 106 to the identification system 112 on the line 108, and the amplified output signal from the light-responsive element 104 is coupled through the amplifier section 106 to the identification system 112 on the line 110. The identification system 112 decodes the output signals that are coupled to it on the lines 108 and 110, and it provides a binary data signal that is representative of these output signals to the data utilization device 114 on the line 113. The data utilization device 114 may be coupled to a display device or a recording device 116, which, for example, may be a cash register having a display section.

The video processing section 115 of FIG. 4 is coupled to the lines 108 and 110 to receive the noninfrared and the infrared signal components from the light-responsive elements 102 and 104 of FIG. 2, respectively. The video processing section 115 converts the two input signals which appear on the lines 108 and 110 into three binary output signals, which represent "white," "green," and "black" signals and which appear on the lines 120, 122, and 124, respectively. An output signal appears on the line 120 when both of the light-responsive elements 102 and 104 are receiving predetermined amounts of light. An output signal appears on the line 122 when only the light-responsive element 104 is receiving a predetermined amount of light. An output signal appears on the line 124 when neither of the light-responsive elements 102 or 104 is receiving predetermined amounts of light.

The decoding section 126 of FIG. 4 receives the "white," "green," and "black" signals from the video processing section 115, and it decodes these signals and provides a corresponding logic level "1" or a logic level "0" signal to the input register section 128. Data is temporarily stored in the input register section 128 after it has been decoded by the decoding section 126, since data can be transferred into the memory section 130 only at a predetermined time.

The memory section 130 in the disclosed embodiment consists of a five-bit auxiliary memory shift register 132, which is coupled to the output stage of the input register section 128. The memory register 134 is coupled between the output stage of the auxiliary memory register 132 and the input stage of the eight-bit output register 148. The memory register 134 may be a 128-bit metal-oxide-semiconductor shift register or other type of shift register. A total of 133 bits may, therefore, be stored in the memory section 130, and labels containing up to 30 digits of data of four bits per digit may, therefore, be employed. The memory section 130 is so constructed that new data may be transferred from the auxiliary memory register 132 into the memory register 134, or, alternately, old data in the memory register 134 may be recirculated.

The memory input synchronization section 136 is coupled to the input register section 128, to the end-of-label detection section 138, to the comparison section 147, and to the program counter section 140. It receives input signals from the end-of-label detection section 138, from the comparison section 147, and from the program counter section 140, which enable it to control the transfer of data into the auxiliary memory register 132 at the proper time according to the number of bits of information that are encoded on the label 20.

The probe 62 of FIG. 2 may traverse the label 20 at various speeds; for example, the speed of the probe 62 in traversing the label 20 may be from 3 to 60 inches per second or more, and, therefore, it is necessary to provide some means of determining when the probe 62 has completely traversed the label 20. The end-of-label detection section 138 performs this function by generating an "end-of-label" signal whenever the probe 62 travels across a white portion of the label 20, which is at least four times as wide as the last colored bar of the label 20 that was traversed by the probe 62. After the "end-of-label" signal is generated by the end-of-label detection section 138, data that is contained in the memory section 130 and in the output register 148 is checked to determine whether or not the information bits that have been sensed and decoded represent valid information.

The last five bits of the label 20 which are sensed are decoded are the four "size code" bits and a "direction" bit, and these bits are stored in the auxiliary memory register 132. The "size code" bits that are stored in the auxiliary memory register 132 are compared with the "size code" bits that are stored in the output register 148 by the comparison section 147 following the generation of an "end-of-label" signal by the end-of-label detection section 138. If these two numbers are equal, a signal is supplied to the parity section 146 to initiate a parity check of the data that is stored in the memory register 134. A valid parity check occurs whenever the sum of the "1" bits that are stored in the memory register 134 are equal to the sum of the "0" bits that are stored in the memory register 134. The stored bits are summed on a module 3 basis (that is, only the numbers 0, 1, and 2 are allowed in the sum, and, when 1 is added to 2, the result is 0).

The program counter section 140 contains a seven-bit program counter, which can count to 128, and this program counter increments its count once each time that data is shifted one position in the memory register 134. A control signal from the program counter section 140 is supplied to the memory input synchronization section 136 to insure that data bits are transferred from the input register section 128 to the auxiliary memory register 132 only when the program counter in the program counter section 140 is in a count range of 127 through 007. A count of 127 is the maximum count stage of the program counter, which goes to a count stage of 000 following the count of 127.

The output register 148 is coupled to the memory register 134 and transmits data to the data utilization device 114 of FIG. 2. The output register 148 is a shift register which receives incoming information bits in one direction but which can transmit the information bits to the data utilization device 114 in either a forward or a reverse direction, in accordance with the direction in which the probe 62 scanned the label 20 when the data was being sensed and decoded.

The clock 127 of FIG. 4 is a conventional clock system, and, in the disclosed embodiment, it supplies two master clock signal trains, which are designated as the "clock 1" and "clock 3" signals, respectively, to various sections of the identification system. The "clock 1" and "clock 3" signals have the same pulse repetition rate, but they are displaced in time relative to one another. The "clock 1" and "clock 3" signals correspond to the clock signals that are required by the conventional metal-oxide-semiconductor four-phase memory shift register 134, and they may be provided by the date utilization device 114.

A schematic of the video processing section 115 of FIG. 4 is shown in FIGS. 5A, 5B, and 5C. When the dotted lines 5--5 of FIGS. 5A and 5B and 5'--5' of FIGS. 5B and 5C overlap, a complete schematic diagram of the video processing section 115 is formed. The video processing section 115 of FIGS. 5A, 5B, and 5C receives two input signals and processes these two input signals to produce three digital output signals each of which is representative of one color of the colored bars of the label 20.

The light-responsive elements 102 and 104 are preferably photodiodes which are operated in the reverse-biased mode, so they sense the noninfrared and the infrared light-signal components of the incident light, respectively, from the dichroic mirror 100 of FIG. 2. The cathode of the photodiode 102 is connected to the terminal 701, which is coupled to a positive voltage supply. The anode of the photodiode 102 is connected to the gate of the field effect transistor 703. The drain of the field effect transistor 703 is connected to the terminal 705, which is coupled to a positive voltage supply. The source of the field effect transistor 703 is connected to the positive input terminal of the operational amplifier 707. The positive input terminal of the operational amplifier 707 is also connected to the resistor 709, which in turn is connected to the terminal 711, which is coupled to a negative voltage supply.

The resistor 713 is connected to the terminal 716, which is coupled to a negative voltage supply, and to the resistor 715, which also is connected to the anode of the photodiode 102 and to the gate of the field effect transistor 703. The resistor 717, which is connected between the output of the operational amplifier 707 and the negative input terminal of the amplifier 707, is the required feedback resistor. The resistor 719 is connected between the negative input terminal of the amplifier 707 and an earth potential. Therefore, whenever a noninfrared light-signal component is sensed by the photodiode 102, a signal is coupled through the field effect transistor 703 to the positive input terminal of the operational amplifier 707, and the operational amplifier 707 produces a positive polarity output signal that is proportional to the incident noninfrared light-signal component.

The resistor 720 is connected between the output of the operational amplifier 707 and the negative input terminal of the operational amplifier 721. The resistor 722, which is connected between the output and the negative input terminals of the operational amplifier 721, is the required feedback resistor. The resistor 723 is connected from the positive input terminal of the amplifier 721 to an earth potential. Therefore, whenever an output signal appears from the amplifier 707, this signal is inverted, and a negative polarity output signal is produced by the amplifier 721.

The waveform 724 represents the electrical signal that is connected to the positive input terminal of the amplifier 707 when the sensing probe 62 scans a white colored bar first, then a black colored bar, and finally a green colored bar. The waveform 725 represents the electrical signal that is produced at the output of the amplifier 721 when an electrical signal having the waveform 724 is supplied to the positive input terminal of the amplifier 707. The most positive potential level of the waveform 725 is termed the "black level."

The resistor 726 is connected between the output of the amplifier 721 and the anode of the diode 727, and the cathode of the diode 727 is connected to the resistor 728, which is also coupled to an earth potential. The cathode of the diode 727 is also connected to the gate of the field effect transistor 729 and to one end of the capacitor 730, the other end of which is coupled to an earth potential. The drain of the field effect transistor 729 is connected to the terminal 731, which is coupled to a positive voltage supply. The source of the field effect transistor 729 is connected to the resistor 732, which is also connected to the junction point of the resistors 715 and 713.

When the waveform 725 is at a positive potential level, the capacitor 730 receives charging current through the resistor 726 and the forward-biased diode 727. The charge on the capacitor 730 controls the field of effect transistor 729, and, as current varies through the resistor 732, the bias voltage on the gate of the field effect transistor 703 also varies to compensate for long term changes in the intensity of the incident light signal or the "black level." The resistor 728 substantially determines the discharge time constant for the capacitor 730, which may be, for example, approximately 2 seconds when the speed of the probe is between 3 and 60 inches per second. The discharge time of the capacitor 730 corresponds to the time required to scan an entire label.

The resistor 733 is connected between the output of the amplifier 721 and the anode of the diode 734. The cathode of the diode 734 is connected to the base of the PNP-transistor 735. The transistor 735 operates as an emitter-follower, and it has its collector coupled to the terminal 820, which is coupled to a negative voltage supply, and its emitter connected to the resistor 736, which is also connected to the terminal 737, which in turn is coupled to a positive power supply. The base of the transistor 735 is also connected to the bias resistor 738, which is connected to the terminal 739, which is coupled to a negative voltage supply. The junction point of the base of the transistor 735 and the resistor 738 is also connected to one end of the capacitor 740, the other end of which is coupled to an earth potential. The output signal from the amplifier 721 is coupled through the resistor 733 and the diode 734 when the signal has a positive polarity, and it charges the capacitor 740 to a "black level" that is related to the waveform 725. The discharge time of the capacitor 740 may be, for example, 2 milliseconds, which corresponds to the time required for the scanning of one colored bar, and, therefore, the "black levels" that are associated with the capacitors 730 and 740 are related levels but not identical levels.

The operational amplifier 741 has its positive terminal connected to the resistor 742, which is also connected to the terminal 743, which is coupled to a positive voltage supply. The resistor 744 is also connected between the positive input terminal of the operational amplifier 741 and the output terminal of the operational amplifier 721. The negative input terminal of the amplifier 741 is connected to the resistor 745, which is also connected to the emitter of the transistor 735. The resistor 746, which is connected between the negative input terminal and the output terminal of the amplifier 741, is the requires feedback resistor. The operational amplifier 741, therefore, subtracts the "black level," which is stored by the capacitor 740, from the signal which is represented by the waveform 725, to produce an output signal which is represented by the waveform 747.

The amplifiers 748, 749, and 759 operate in a manner that is analogous to the manner of operation of the amplifiers 707, 721, and 741. When the sensing probe 62 has traversed a white colored bar, then a black colored bar, and finally a green colored bar, the waveform 750 is produced and is coupled to the positive input terminal of the amplifier 748. The waveform 750 is inverted by the amplifier 749, which produces the waveform 751 as an output signal. The waveform 750 is at a positive polarity level that is proportional to the infrared light-signal component of the incident light. The most positive polarity portion of the waveform 751 results in a storage of a "black level" signal in the capacitor 752, which varies the bias level of the field effect transistor 753, which is connected to the input of the amplifier 748 to compensate for long term changes in the intensity of the incident light.

The output signal of the amplifier 749 is coupled through the resistor 754 and the diode 756 to the NPN-transistor 757, which functions as an emitter-follower. Since the diode 756 is reversed with respect to the diode 734, the capacitor 758, which is connected to the anode of the diode 756, receives charging current when the output of the amplifier 749 is at a negative potential level. The most negative voltage potential level of the output of the amplifier 749, which corresponds to the waveform 751, is termed the "white level" for the waveform 751, and this level is stored in the capacitor 758.

The resistor 760 is connected between the junction point of the base of the transistor 757 and one end of the capacitor 758 and the terminal 761, which is coupled to a positive power supply. The collector of the transistor 757 is connected to the terminal 762, which is coupled to a positive power supply, and the emitter of the transistor 757 is coupled to the resistor 763, which in turn is connected to the terminal 814, which is coupled to a negative voltage supply. The resistor 764 is connected between the emitter of the transistor 757 and the positive input terminal of the operational amplifier 759. The resistor 765 is connected between the terminal 766, which is coupled to a positive voltage supply and the positive input terminal of the amplifier 759. The resistor 767, which is connected between the output terminal and the negative input terminal of the amplifier 759, is the required feedback resistor. The resistor 769 is connected between the negative input terminal of the amplifier 759 and the output terminal of the amplifier 749. The amplifier 759 subtracts the signal which is represented by the waveform 751 from the "white level" signal that is stored in the capacitor 758 to produce the output signal which is represented by the waveform 768.

The diode 816 is connected with its cathode connected to the resistor 770, which is also coupled to the terminal 771, which is coupled to a positive voltage power supply. The diode 772 is connected with its cathode connected to the output of the amplifier 759 and with its anode connected to the output of the amplifier 759 and with its anode connected to the junction point of the resistors 770 and 773 and the anode of the diode 816. The resistor 773 is also connected to one end of the capacitor 774, the other end of which is coupled to an earth potential. The NPN-transistor 775 has its base connected to the junction point of the capacitor 774 and the resistor 773, and its collector connected to the terminal 776, which is coupled to a positive voltage power supply. The emitter of the transistor 775 is coupled to the resistor 777, which is also coupled to the terminal 778, which is coupled to a negative voltage supply.

The capacitor 774 acquires a charge which develops a reference potential that is representative of the most negative polarity excursion of either of the waveforms 747 and 768. This reference potential is proportional to the strength of the input signal to insure that the video processing section is sensitive to signals which are received from labels of different reflective attributes. The transistor 775 produces an output signal which is proportional to the voltage across the capacitor 774, and this output signal represents a threshold voltage which is determined by the ratio of the resistors 794 and 796 and is then coupled to the output amplifiers 779, 780, and 781 via the resistors 795, 797, and 798.

The resistor 783 is connected to the terminal 784, which is coupled to a positive voltage supply, and it is also connected to the positive input terminal of the operational amplifier 782. The resistor 785 is connected to the positive input terminal of the amplifier 782, and it is also connected to the output terminal of the amplifier 749. The resistor 787 is connected between the negative input terminal of the amplifier 782 and the output terminal of the amplifier 721. The resistor 789, which is connected between the output and the negative input terminals of the amplifier 782, is the required feedback resistor. Signals which are proportional to the output signals of the amplifier 721 are, therefore, subtracted from the output signal from the amplifier 749, and the waveform 788 is produced by the amplifier 782.

The resistor 790 is connected to the terminal 812, which is coupled to a positive voltage supply, and it is also connected to the anode of the diode 791. The cathode of the diode 791 is connected to the junction point of the cathode of the diode 792 and the resistor 793. The resistor 793 is also connected to an earth potential, and the anode of the diode 792 is coupled to the junction point of the resistors 794, 795, 796, 797, and 798. The resistors 790 and 793, in conjunction with the diodes 791 and 792, develop a fixed minimum threshold voltage, which is useful when faulty labels are being traversed by the sensing probe or when the probe 62 has just begun to traverse a data-encoded label 20 and steady-state conditions are not yet established.

The resistor 797 is connected to the positive input terminal of the amplifier 779, the resistor 795 is connected to the positive input terminal of the amplifier 780, and the resistor 798 is connected to the positive input terminal of the amplifier 781, and a threshold signal that is provided by the resistors 796 and 794 and the minimum threshold voltage is thereby coupled to the amplifiers 779, 780, and 781, respectively.

The resistor 799 is connected between the negative input terminal of the amplifier 779 and the output terminal of the amplifier 741. The resistor 800 is connected between the negative input terminal of the amplifier 781 and the output terminal of the amplifier 759. The resistor 801 is connected between the negative input terminal of the amplifier 780 and the output terminal of the amplifier 782. The resistors 799, 800, and 801 couple signals from the amplifiers 741, 759, and 782, respectively, to the amplifiers 779, 781 and 780, respectively.

The diode 802 has its cathode connected to the negative input terminal of the amplifier 779 and its anode connected to the positive input terminal of the amplifier 779. The diode 803 has its anode connected to the negative input terminal and its cathode connected to the positive input terminal of the amplifier 779. A "white" digital signal appears on the output terminal of the amplifier 779 whenever the difference between the threshold signal which is present on its positive input terminal and the output signal from the amplifier 741 which is present on its negative input terminal exceeds a predetermined amount.

The diodes 804 and 805 are connected across the input terminals of the amplifier 780, and the diodes 806 and 807 are connected across the input terminals of the amplifier 781.

Digital output signals are achieved by the amplifiers 779, 780, and 781, through the elimination of the feedback resistor. The amplifier 779 produces the "white" signal, the amplifier 780 produces the "green" signal, and the amplifier 781 produces the "black" signal, as indicated in FIG. 5C by the letters, W, G, and B, respectively.

The resistor 810 of FIG. 5A is connected between the negative input terminal of the amplifier 721 and the output terminal of the amplifier 749. The resistor 811 is connected between the negative input terminal of the amplifier 749 and the output terminal of the amplifier 721. The resistors 810 and 811 are employed, since the conventional dichroic, mirror 100 of FIG. 2 may not completely split the incoming signal into pure infrared and noninfrared light-signal components, but, instead, it may allow a small amount of the infrared light-signal component to be received by the photodiode 102, and a small amount of the noninfrared signal component to be received by the photodiode 104. The resistors 810 and 811, by coupling a portion of the output signal from the amplifier 721 to the negative input terminal of the amplifier 749 and a portion of the input signal from the amplifier 749 to the negative input terminal of the amplifier 721, provide a means of obtaining substantially pure noninfrared and infrared signals.

The logic portion of the identification system may be separated into functional blocks. The major functions performed by the logic are (1) decoding of video signals into binary bits; (2) storage of the decoded bits; (3) identification of a label; (4) validation of the label contents; and (5) output of the data bits to a terminal control unit, cash register, data processor, or other data utilization device.

The decoding section 126 of FIG. 4 converts the "black," "green," and "white" signals from the video processing section 115 into binary "1"'s and binary "0"'s. Signals for a representative sequence of color transitions are shown in FIG. 18. The logic consists of flip-flop elements that remember a first colored bar until a second colored bar is sensed. When the first and second colored bars are different, a "data strobe" signal is generated, indicating that a color transition has occurred. The "date line" signal is generated by decoding the first and second colored bars to define binary "1"'s and binary "0"'s. The second colored bar is remembered by a flip-flop until the next colored bar is sensed.

Whenever a "data strobe" signal is generated by the decoding logic, the binary bit on the data line is stored in an input register in the input register section 128. This register is used because the data is sensed randomly, but it can be transferred to the main memory only at a particular time. The size of this register is dependent upon the access time of the main memory, and, in the described embodiment, the input register is an eight-bit register. The size of the memory register 134 is dependent upon the maximum size of label to be sensed, and, in the described embodiment, it is a 128-bit dynamic shift register.

The program counter section 140 contains a seven-bit program counter, which keeps track of the data in the memory. The program counter increments once every bit time which corrresponds to data being shifted one position in the memory. Whenever new data is scanned and the memory already contains previously stored data, new information bits must be placed in the memory into the bit positions which follow the information that was previously stored in the memory. The program counter performs this function in conjunction with the memory input synchronization section 136.

New data can be transferred into the memory register 134 only at a particular time, which in this embodiment is when the program counter is in a "0" count state. Whenever new data bits are written into the memory, the program counter is reset to a "0" count state at the moment that the last bit is written in. Whenever the program counter approaches a "0" count state, the input register is examined to determine the number of new data bits that have been sensed since the last time that the program counter was in a "0" count state.

In the example of FIG. 19, three new data bits have been sensed, and they are shifted to the output stage of the input register. When the program counter reaches a "0" count state, the three data bits in the input register are shifted into the auxiliary memory register 132, and the three rightmost bits in the auxiliary memory register 132 are shifted into the memory register 134. After the data is shifted three positions (three-bit times), the input register does not contain any data bits, and the program counter is reset to a "0" count state. Resetting the program counter at the moment that the last bit is written into the memory register 134 automatically provides the required synchronization. The transfer of data from the input register to the auxiliary memory register 132 and to the memory register 134 occurs whenever the input register contains new data bits and the program counter is in a "0" count state but the end of the label has not been detected.

The auxiliary memory register 132 always contains the last five data bits that have been sensed by the probe 62. The value of the data bits that are stored in the auxiliary memory register 132 is compared with the count of the program counter to determine the time for examining the data bits that are stored in the output register 148. If this comparison is made, the "size code" bits that are stored in the auxiliary memory register 132 are compared with the "size code" bits that are stored in the output register 148, and, if they are equal, a valid label format signal is generated, which initiates a module 3 parity check.

A module 3 parity check is performed for every valid label that is detected. Consequently, the sum of the "1" bits must be equal to the sum of the "0" bits on a module 3 basis. The table below shows the required characteristics for the module 3 parity check for various labels which contain different numbers of data bits. ---------------------------------------------------------------------------

MODULE 3 PARITY CHARACTERISTICS Total Module 3 Counters Digits Bits Sum 1's Sum 0's __________________________________________________________________________ 2 20 1 1 4 28 2 2 6 36 0 0 8 44 1 1 10 52 2 2 12 60 0 0 14 68 1 1 16 76 2 2 18 84 0 0 20 92 1 1 22 100 2 2 24 108 0 0 26 116 1 1 28 124 2 2 30 132 0 0 __________________________________________________________________________

A module 3 parity check will detect any single-bit error and multiple errors of the same type that are not multiples of three. It will not detect counteracting errors such as a "0" read as a "1" and a "1" read as a "0."

Whenever a valid label has been detected and the module 3 parity-checking logic indicates that the sensed data bits are valid, the data bits are sent to a data utilization device. The output register 148 is a five-bit shift register that is capable of shifting either left or right. Data bits are always loaded into the output register 148 by shifting right, and, when data bits are transferred to the data utilization device, the direction of shifting of these bits is determined by the value of a "direction" bit that is sensed from the label. If a label was read from right to left, instead of left to right, all the sensed data bits are complemented and are transmitted from the output register 148 to the data utilization device in a reverse sequence to that in which they were read into the output register 148.

FIGS. 6A and 6B, when overlapped along the lines 6--6, form a block diagram of the decoding section 136 of FIG. 4. The inverters 182, 184, and 186 are coupled to the lines 120, 122, and 124, respectively. The NAND-gate 188 has a first input terminal coupled to the line 120, a second input terminal coupled to the output terminal of the inverter 184, and a third input terminal coupled to the output terminal of the inverter 186. The NAND-gate 188 will, therefore, produce a logic level "0" output signal whenever a "white" signal is present on the line 120 and "green" and "black" signals are not present on the lines 122 and 124, respectively. The inverter 190 inverts the signal from the NAND-gate 188, and, therefore, the inverter 190 produces a logic level "1" output signal when a "white" signal is present on the line 120 and "green" and "black" signals are not present on the lines 122 and 124, respectively.

In a similar manner, the NAND-gate 192 and the inverter 194 cause a logic level "1" output signal to be produced by the inverter 194 when a "green" signal is present on the line 122, and "black" and "white" signals are not present on the lines 120 and 124, respectively. The NAND-gate 196 and the inverter 198 cause a logic level "1" output signal to be produced by the inverter 198 when a "black" signal is present on the line 124 and "white" and "green" signals are not present on the lines 120 and 122, respectively.

The NAND-gate 200 has a first input terminal coupled to the output terminal of the inverter 190 and a second input terminal coupled to the output terminal of the inverter 267 of FIG. 6B to receive the "transition inhibit" signal from the inverter 267. The "transition inhibit" signal prevents the storage of new data in the memory section 130 of FIG. 4 in the event that the data of a previously sensed label that is stored in the memory section 130 has not yet been supplied to the data utilization device 114 of FIG. 2, and it also delays the initial sensing of a new data bit for a predetermined time--for example, 100 microseconds--until transitory noise signals have subsided.

The output terminal of the NAND-gate 200 is coupled to the C, or unconditional clear, input terminal of the flip-flop 205, which is representative of all of the conventional flip-flops that are employed in the identification system. The truth table for the flip-flop 205 and the other flip-flops that are employed in the disclosed identification system is shown below: ---------------------------------------------------------------------------

FLIP-FLOP TRUTH TABLE J.sub.n K.sub.n Q.sub.n .sub.+ 1 __________________________________________________________________________ 0 0 Q.sub.n (no change) 1 0 1 (set) 0 1 0 (clear) 1 1 Q.sub.n .sub.+ 1 (change regardless of previous state) __________________________________________________________________________

(where n represents the clock time and it may assume the values of 0, 1, 2, 3, . . . etc.).

Signals appearing on the J and the K input terminals of a flip-flop determine the state of the flip-flop according to the defined truth table. When the C, or unconditional input, terminal of a flip-flop is at a logic level "0," the flip-flop is unconditionally cleared. When the P, or preset, input terminal is at a logic level "0," the flip-flop is unconditionally set.

The flip-flop 205 will be driven into an unconditional clear state, in which its Q output terminal is at a logic level "0" and its Q output terminal is at a logic level "1," when the output of the NAND-gate 200 is at a logic level "0." The output terminals of the NAND-gates 202 and 204 are coupled to the C input terminals of the flip-flops 206 and 207, respectively. The clock input terminals of the flip-flops 205, 206, and 207 are coupled to receive the "white reset," the "green reset," and the "black reset" signals, respectively. When the "transition inhibit" signal is at a logic level "1," it drives the output terminal of the NAND-gate 200 to a logic level "0" if a logic level "1" signal is also present on the output terminal of the inverter 190. When the "transition inhibit" signal goes to the logic level "0," the NAND-gates 200, 202, and 204 can no longer provide a logic level "0" clear signal to the flip-flops 205, 206, and 207, respectively.

The K input terminal of the flip-flop 205 is at a logic level "0," since it is connected to an earth potential. The J input terminal of the flip-flop 205 is unconnected, which is equivalent to placing a constant logic level "1" signal on it. Therefore, when a logic level "1" "white reset" signal appears on the clock input terminal and a logic level "1" signal simultaneously appears on the C input terminal, the flip-flop 205 is driven into a set state. The Q output terminal of the flip-flop 205, which is coupled to the J input terminal of the flip-flop 210 and to the C input terminal of the flip-flop 212, is at a logic level "1" when the flip-flop 205 is in a clear state, and it is at a logic level "0" when the flip-flop 205 is in a set stage. The signal on the Q output terminal of the flip-flop 205 is designated as the "white latch" signal.

Initially, before a white colored bar has been traversed by the probe 62, a logic level "0" signal is supplied to the J input terminal of the flip-flop 210 by the Q output terminal of the flip-flop 205, and the flip-flop 210 is driven into a clear state when a logic level "1" "clock 1" signal is simultaneously supplied to its clock input terminal, since the K input terminal of the flip-flop 210 is unconnected. When the flip-flop 205 is driven into a clear state by the NAND-gate 200, its Q output terminal supplies a logic level "1" signal to the J input terminal of the flip-flop 210, and, when a logic level "1" "clock 1" signal is simultaneously supplied to the clock input terminal of the flip-flop 210, the flip-flop 210 will be driven into a set state. When the flip-flop 210 is in a set state, the Q output terminal of the flip-flop 210 is at a logic level "1," and the Q output terminal of the flip-flop 210 is at a logic level "0." The signal on the Q output terminal of the flip-flop 210 is designated as a "white pulse" signal, and the signal on the Q output terminal of the flip-flop 210 is designated as a "white pulse" signal.

When the flip-flop 205 is driven into a clear state by the NAND-gate 200, a logic level "1" signal is also coupled to the C input terminal of the flip-flop 212. The J input terminal of the flip-flop 212, which is coupled to the Q output terminal of the flip-flop 210, is at a logic level "1" when the flip-flop 210 is in a set state. Since the flip-flop 212 was initially driven into a clear state by the initial logic level "0" output signal of the Q output terminal of the flip-flop 205, the Q output terminal of the flip-flop 212, which is coupled to its K input terminal, is initially at a logic level "1." The appearance of a logic level "1" "clock 1" signal on the clock input terminal of the flip-flop 212 will, therefore, drive the flip-flop 212 into a set state. When the flip-flop 212 is in a set state, its Q output terminal, which is coupled to the C input terminal of the flip-flop 210, is at a logic level "0," and the flip-flop 210 is driven back into a clear state. When the flip-flop 205 receives a logic level "1" "white reset" signal on its clock input terminal, it is driven back into a set state, and initial conditions are reestablished.

When a green colored bar is being traversed by the sensing probe 62, the flip-flops 206, 214, and 216 function in a manner identical to the manner in which the flip-flops 205, 210, and 212 function when a white colored bar is being traversed by the sensing probe 62. When a black colored bar is being traversed by the sensing probe 62, the flip-flops 207, 218, and 220 function in a manner identical to the manner in which the flip-flops 205, 210, and 212 function when a white colored bar is being traversed by the sensing probe 62.

The NAND-gates 222 through 238 of FIG. 6B receive the appropriate color latch and color pulse signals from the flip-flops 205 through 220. For example, the NAND-gate 222 receives a "green pulse" signal from the Q output terminal of the flip-flop 214, and it also receives a "black pulse" signal from the Q output terminal of the flip-flop 218. A logic level "1" output signal from the NAND-gate 222, therefore, indicates that either a "green pulse" signal or a "black pulse" signal is being produced. In a similar manner, the NAND-gate 224 produces a logic level "1" output signal whenever a "white pulse" signal or a "black pulse" signal is produced, and the NAND-gate 226 produces a logic level "1" output signal whenever a "white pulse" or a "green pulse" signal is produced.

The output signals from the NAND-gates 222, 224, and 226 are supplied to the NAND-gates 240, 250, and 254 to develop the "white reset," the "green reset," and the "black reset" signals, respectively. The output terminal of the NAND-gate 222 is coupled to a first input terminal of the NAND-gate 240, the output terminal of the NAND-gate 224 is coupled to a first input terminal of the NAND-gate 250, and the output terminal of the NAND-gate 226 is coupled to a first input terminal of the NAND-gate 254. Each of the NAND-gates 240, 250, and 254 also receives the "transmission valid" signal from the control section 142 of FIG. 4. The "transmission valid" signal is at a logic level "1" whenever video signals are being transmitted from the video processing section 115 of FIG. 4 to the decoding section 126 of FIG. 4.

During the time that the signals are being transmitted from the video processing section 115 to the decoding section 126, the NAND-gate 240 produces a logic level "0" output signal whenever a "green pulse" signal or a "black pulse" signal is produced. The NAND-gate 242 has a first input terminal, coupled to the clock to receive the "clock 1" signal, and a second input terminal, coupled to receive the "transmission valid" signal. The NAND-gate 242 will, therefore, produce a logic level "1" output signal whenever information is being transmitted from the video processing section 115 to the decoding section 126, since the "transmission valid" signal is at a logic level "0" at this time. However, when information is not being transmitted from the video processing section 115 to the decoding section 126, the NAND-gate 242 produces a logic level "0" output signal upon the occurrence of a logic level "1" "clock 1" signal.

The first input terminal of the NAND-gate 246 is coupled to the output terminal of the NAND-gate 240, and a second input terminal of the NAND-gate 246 is coupled to the output terminal of the NAND-gate 242. The NAND-gate 242, therefore, causes the NAND-gates 246, 252, and 256 to generate reset signals to the flip-flops 205 through 207 when the probe 62 has transversed the entire label, including a colored portion at the end of the label, which is at least four times as wide as the last colored bar of the label.

In a similar manner, the NAND-gate 252 produces a logic level "1" "green reset" signal whenever a "white pulse" or a "black pulse" logic level "1" signal is produced and the "transmission valid" signal is at a logic level "1." The NAND-gate 256 similarly produces a logic level "1" "black reset" signal whenever a "white pulse" or a "green pulse" logic level "1" signal is produced and the "transmission valid" signal is at a logic level "1."

If the flip-flop 205 has been driven into a clear state by the presence of a "white" signal on the line 120, the flip-flop 205 will remain in a clear state until a "green pulse" signal or a "black pulse" signal is produced, and the NAND-gate 246 produces a logic level "1" "white reset" signal. When the logic level "1" "white reset" signal is supplied to the clock input terminal of the flip-flop 205, the flip-flop 205 is driven back into a set state if a logic level "1" signal is simultaneously supplied to its C input terminal by the NAND-gate 200.

The NAND-gates 228 through 238 are coupled to the flip-flops 205 through 220 to receive the various color latch and color pulse signals that are produced by these flip-flops. The NAND-gate 228 has the "green latch" and the "black pulse" signals coupled to its input terminals, and, therefore, the NAND-gate 228 produces a logic level "0" when the "green latch" and the "black pulse" signals are simultaneously at a logic level "1." The "white latch" and the "green pulse" signals are coupled to the input terminals of the NAND-gate 230 and the "black latch" and the "white pulse" signals are coupled to the input terminals of the NAND-gate 232. Logic level "0" output signals are, therefore, produced by the NAND-gates 228, 230, and 232 whenever their respective inputs are simultaneously at a logic level "1." The output terminals of the NAND-gates 228, 230, and 232 are supplied to the input of the NAND-gate 258, and the output terminal of the NAND-gate 258 is, therefore, at a logic level "1" whenever the output terminals of any of the NAND-gates 228, 230, or 232 are at a logic level "0." The input terminal of the inverter 260 is coupled to the output terminal of the NAND-gate 258, and it inverts the signal that it receives from the NAND-gate 258.

As the probe 62 traverses the data-encoded label 20, the appearance of a green colored bar produces a logic level "1" "green latch" signal, and, if a black colored bar is encountered next, a logic level "1" "black pulse" signal is subsequently produced, which signifies that a "0" bit has been detected. When a "0" bit is detected, the output of the inverter 260 goes at a logic level "0." The NAND-gates 234, 236, and 238 have their outputs coupled to the input terminals of the NAND-gate 262, which has its output terminal coupled to the input terminal of the inverter 264. The "white latch" and the "black pulse" signals are coupled to the input terminals of the NAND-gate 234, the "black latch" and the "green pulse" signals are coupled to the input terminals of the NAND-gate 236, and the "green latch" and the "white pulse" signals are coupled to the input terminals of the NAND-gate 238. The output terminal of the inverter 264 will, therefore, be at a logic level "1" when a "0" bit has been detected. Conversely, the output terminal of the inverter 260 will be at a logic level "1" and the output terminal of the inverter 264 will be at a logic level "0" when a "1" bit has been detected.

The NAND-gates 266 and 268 are cross-coupled to form a NAND-gate latch circuit, and, therefore, when a "1" bit has been detected, the logic level "1" output signal of the inverter 260 and the logic level "0" output signal of the inverter 264 will drive the NAND-gate 266 into a "0" state and the NAND-gate 268 into a "1" state. When the NAND-gate 268 is in a "1" state, a logic level "1" "data line" signal appears on its output terminal. On the other hand, when a "0" bit has been detected, the logic level "1" output signal from the inverter 264 and a logic level "0" output signal from the inverter 260 drives the NAND-gate 266 into a "1" state and the NAND-gate 268 into a "0" state, and a logic level "0" "data line" signal will appear on the output terminal of the NAND-gate 268 in this instance. The output terminals of the inverters 260 and 264 are also coupled to the input terminals of the NAND-gate 270, the output terminal of which is coupled to the input terminal of the inverter 272. Thus, whenever a "1" or a "0" bit has been detected, the output terminal of the NAND-gate 270 is at a logic level "1," and the output terminal of the inverter 272 is at a logic level "0." If neither a "1" nor a "0" bit has been detected, the output terminals of the inverters 260 and 264 will both be at a logic level "0," and the inverter 272 will also be at a logic level "0." The output signal from the inverter 272 is termed the "data pulse" signal.

The NAND-gates 274 and 276 are cross coupled to form a NAND-gate latch, and the output signal of the NAND-gate 274 is termed the "data valid" signal, while the output signal of the NAND-gate 276 is termed the "data valid" signal. When the output terminal of the inverter 272 is at a logic level "0," the NAND-gate 274 is driven into a "1" state, and the NAND-gate 276 is driven into a "0" state if the "reset data valid" signal from the input register section 128 of FIG. 4 is simultaneously at a logic level "1." The "reset data valid" signal can conditionally go to a logic level "0" only when the "clock 1" signal is at a logic level "1." The "reset data valid" signal is at a logic level "1" at other times.

The output terminal of the inverter 308 is coupled to an input terminal of the NAND-gate 261, which is cross coupled with the NAND-gate 263 to form a NAND-gate latch circuit. The NAND-gate 299, receives the "white pulse," the "green pulse," and the "black pulse" signals on its input terminals, and, therefore, a logic level "1" output signal from the NAND-gate 299 signifies a "color pulse" signal. The fourth stage of the counter 310 of FIG. 8 produces the "delayed reset" signal, and this signal is coupled to the input terminal of the NAND-gate 263. Whenever the output of the NAND-gate 299 is at a logic level "1" and the "clock 1" signal is simultaneously at a logic level "1," a logic level "1" "reset 310" signal is produced by the NAND-gate 306 of FIG. 8 to reset the counter 310. Thus, upon the occurrence of a logic level "1" "color pulse" signal, the NAND-gate 261 is driven into a "1" state, and the NAND-gate 263 is driven into a "0" state, since the "delayed reset" signal is at a logic level "1" at this time.

The counter 310 of FIG. 8 increments once each time that the NAND-gate 320 supplies a logic level "1" "increment 310" pulse to the increment input terminal of the counter 310. A logic level "0" "delayed reset" signal will, therefore, occur after the "reset 310" signal has gone to a logic level "0." For example, it may occur 100 microseconds after the "reset 310" signal has returned to a logic level "1." When the "color pulse" signal is at a logic level "1," the output terminal of the inverter 308 is at a logic level "0," and, if the "delayed reset" signal also is at a logic level "1," the NAND-gate 263 will be driven into a "0" state, and the NAND-gate 261 will be driven into a "1" state.

The output terminal of the NAND-gate 263 is coupled to a first input terminal of the NAND-gate 265, and a second input terminal of the NAND-gate 265 is coupled to the control section 142 of FIG. 4 to receive the "transmission valid" signal. When both of the input signals to the NAND-gate 265 are simultaneously at a logic level "1," the output terminal of the NAND-gate 265 is at a logic level "0," and the logic level "1" "transmission inhibit" signal which is produced by the inverter 267 is coupled to the input terminals of the NAND-gates 200, 202, and 204 of FIG. 6A. The delay of the "transmission inhibit" signal that is provided by the "delayed reset" signal which is coupled to the NAND-gate 263 ensures that transitory noise signals do not affect the identification system when a new information bit is detected.

The NAND-gate 278 in the input register section of FIG. 7 has a first input terminal coupled to the output terminal of the NAND-gate 274 of FIG. 6B to receive the "data valid" signal from the NAND-gate 274. The NAND-gate 278 has a second input terminal, coupled to the clock to receive the "clock 1" signal. The inhibit strobe signal from the memory input synchronization section 136 of FIG. 4 is coupled to the third input terminal of the NAND-gate 278. The "inhibit strobe" signal prevents new data from being entered into the input register 280 during the time that data is being shifted from the input register 280 into the memory section 130 of FIG. 4. Thus, when the "clock 1" signal is at a logic level "1" and the "data valid" signal is at a logic level "1," the output signal from the NAND-gate 278, which is termed the "data strobe" signal, is at a logic level "0" of the "inhibit strobe" signal is also at a logic level "1."

The NAND-gate 290 has a first input terminal, coupled to the clock to receive the "clock 3" signal, and a second input terminal, coupled to the memory input synchronization section 136, to receive the "fast shift latch" signal. The "fast shift latch" signal remains at a logic level "1" for a period of time which is determined by the number of bits stored in the input register 280 which are to be transferred into the memory section 130 of FIG. 4. Each time that a logic level "1" "clock 3" signal occurs when the "fast shift latch" signal is also at a logic level "1," a logic level "0" output signal is produced by the NAND-gate 290.

The output terminals of the NAND-gates 278 and 290 are coupled to input terminals of the NAND-gate 292, and, therefore, a logic level "1" "shift A" signal is produced by the NAND-gate 292 when either of the NAND-gates 278 or 290 is at a logic level "0." The output terminal of the NAND-gate 292 is coupled to the shift input terminal of the input register 280, which is a conventional shift register. Each time the NAND-gate 292 produces a logic level "1" "shift A" output signal, data that is stored in the input register 280 is shifted one storage position toward the output stage of the register.

The NAND-gates 284 and 286 are cross coupled to form a NAND-gate latch circuit. The NAND-gate 282, which has its output terminal coupled to the input terminal of the NAND-gate 284, has a first input terminal, coupled to the clock to receive the "clock 1" signal, and a second input terminal, coupled to the output of the NAND-gate 276 of FIG. 6B to receive the "data valid" signal. Therefore, the output terminal of the NAND-gate 282 is at a logic level "0" only when the "clock 1" signal and the "data valid" signal are simultaneously at a logic level "1."

The "data valid" signal which is coupled to the NAND-gate 278 is at a logic level "0" when the "data valid" signal that is coupled to the NAND-gate 282 is at a logic level "1," and, therefore, the output terminal of the NAND-gate 278 will be at a logic level "1," the NAND-gate 286 will be driven into a "0" state, and the NAND-gate 284 will be driven into a "1" state when the output terminal of the NAND-gate 282 is simultaneously at a logic level "0."

When the "data valid" signal on the input terminal of the NAND-gate 282 is at a logic level "0," the "data valid" signal on the input terminal of the NAND-gate 278 is at a logic level "1." Therefore, if the output of the NAND-gate 282 is at a logic level "1" and the output of the NAND-gate 278 is at a logic level "0," the NAND-gate 284 is then driven into a "0" state, and the NAND-gate 286 is driven into a "1" state, producing a logic level "1" signal on the output terminal of the NAND-gate 286. The NAND-gate 288 has a first input terminal, coupled to the output terminal of the NAND-gate 286, and a second input terminal, coupled to the clock to receive the "clock 1" signal. If the "clock 1" signal is at a logic level "1" when the output of the NAND-gate 286 is simultaneously at a logic level "1," the "reset data valid" signal on the output terminal of the NAND-gate 288 will be at a logic level "0." The "reset data valid" signal is coupled to an input terminal of the NAND-gate 276 of FIG. 6B.

The NAND-gate 294 has a first input terminal, coupled to the output terminal of the NAND-gate 268 of FIG. 6B, which produces the "data line" signal, and a second input terminal, coupled to the memory input synchronization section 136 of FIG. 4 to receive the "inhibit strobe" signal. Therefore, the NAND-gate 294 produces a logic level "0" output signal whenever the inhibit strobe signal and the "data line" signal are simultaneously at a logic level "1." The output terminal of the NAND-gate 294 is coupled to a first input terminal of the NAND-gate 296, and, therefore, when a logic level "0" signal appears on the output terminal of the NAND-gate 294, the NAND-gate 296 produces a logic level "1" "data" signal. The output of the NAND-gate 296 is coupled to the input of the first flip-flop stage of the input register 280. The inverter 204, which is coupled to the output terminal of the NAND-gate 296, supplies a logic level "0" "data" signal to the input terminal of the first flip-flop stage of the input register 280 at this time, when the "data" signal is at a logic level "1." The input register 280 is a conventional shift register, and, each time that a logic level "1" "shift A" signal is supplied to its shift input terminal by the NAND-gate 292, a new data bit is entered into the input register 280, and data already stored in the register is shifted one place toward the output stage of the register.

The output terminal of the NAND-gate 300 is also coupled to an input terminal of the NAND-gate 296. One input terminal of the NAND-gate 300 is coupled to the output terminal of the last flip-flop stage of the input register 280 to receive the "data out" signal, and the other input terminal of the NAND-gate 300 receives the "inhibit strobe" signal from the memory input synchronization section 136 of FIG. 4. Therefore, the NAND-gate 300 produces a logic level "0" output signal whenever the "inhibit strobe" signal is at a logic level "1" and the "data valid" signal is simultaneously at a logic level "1," and data which is stored in the input register 280 is recirculated in the register whenever the "inhibit strobe" signal is at a logic level "1."

The NAND-gate 306 of FIG. 8 supplies the "reset 310" signal to the reset input terminal of the counter 310 to reset the counter 310, as previously described. The NAND-gate 312 has a first input terminal, coupled to the output terminal of the NAND-gate 299 to receive the "color pulse" signal, and a second input terminal, coupled to the clock to receive the "clock 3" signal. The output terminal of the NAND-gate 312 is coupled to the input terminal of the inverter 314, and the output signal from the inverter 314, which is termed the "transfer" signal, is supplied to a first input terminal of each of the NAND-gates 316. A second input terminal of each of the NAND-gates 316 is coupled to the output terminal of one stage of the counter 310. Each of the output terminals of the NAND-gates 316 is coupled to the input of one stage of the counter 318. The NAND-gates 316 transfer the logical inverse of the contents of the eight-bit counter 310 into the eight-bit counter 318 whenever the output of the NAND-gate 312 is at a logic level "0."

The NAND-gate 320 is coupled to the clock to receive the "clock 5" signal from the clock on a first input terminal. The "clock 5" signal has a pulse repetition rate that is less than the pulse repetition rate of the "clock 1" and the "clock 3" signals. For example, the pulse repetition rate of the "clock 5" signal may typically be one-fourth that of the pulse repetition rate of the "clock 1" and the "clock 3" signals. The other input of a NAND-gate 320 is coupled to receive the "transmission valid" signal which is generated in the control section 142 of FIG. 4. The output terminal of the NAND-gate 320 is at a logic level "0" when the "transmission valid" signal and the "clock 5" signals are simultaneously at a logic level "1." The output terminal of the NAND-gate 320 is coupled to the increment input terminal of the counter 310, which is so constructed that a logic level "0" on this terminal causes the counter 310 to increment its count by "1."

The NAND-gate 322 is coupled to the clock to receive the "clock 6" signal on a first input terminal and to the control section 142 to receive the "transmission valid" signal on a second input terminal. The pulse repetition rate of the "clock 6" signal is less than the pulse repetition rate of the "clock 5" signal. For example, the pulse repetition rate of the "clock 6" signal may typically be one-fourth that of the "clock 5" signal. The "clock 2" and "clock 4" signals, which are required for the metal-oxide-semiconductor memory register 134, and the "clock 5" and "clock 6" signals are derived from the "clock 1" and "clock 3" master clock signals in a conventional manner. The output terminal of the NAND-gate 322 is coupled to the increment input terminal of the counter 318, which is so constructed that a logic level "0" on this increment input terminal causes the counter 318 to increment its count by "1."

The counter 310 increments its count once each time that it receives a logic level "0" signal from the NAND-gate 320, while the counter 318 increments its count once each time that it receives a logic level "0" signal from the NAND-gate 322. Since four "clock 5" pulses occur for every "clock 6" pulse that occurs, the counter 318 increments its count at one-fourth of the rate that the counter 310 increments its count. If the counter 318 reaches a state in which all of the stages of the counter are in a "1" state before new information is transferred from the counter 310 into the counter 318, the NAND-gate 324, which is coupled to the outputs of all of the stages of the counter 318, produces a logic level "0" signal. A logic level "0" output signal from the NAND-gate 324 indicates that the probe 62 has traversed a colored portion of the label 20, which is at least four times as wide as the width of the last preceding colored bar. The output terminal of the NAND-gate 324 is coupled to the input terminal of the inverter 325.

It has been determined that, when the hand-held probe 62 is swept across the data-encoded label 20, data is normally received at a rate that is not lower than 5 milliseconds per bit if the operator has been trained to move the probe at a substantially uniform rate. The "clock 5" signal that is supplied to the NAND-gate 320 has a pulse repetition rate such that all the stages of the counter 310 will be in a "1" state 7 milliseconds after the counter 310 has been reset by the "reset 310" signal. Therefore, if a new data bit has not been received during this 7-millisecond period, a logic level "0" signal will appear on the output terminal of the NAND-gate 311, which is coupled to the outputs of all the stages of the counter 310. The output terminal of the NAND-gate 311 is coupled to the input terminal of the inverter 312, which produces the "end-of-transmission" signal on its output terminal.

A first input terminal of the NAND-gate 326 is coupled to the output terminal of the inverter 325, and a second input terminal of the NAND-gate 326 is coupled to the Q output terminal of the flip-flop 328, which produces the "enable after first color" signal. The flip-flop 328 has its K input terminal coupled to an earth potential, and its J input terminal is unconnected. The clock input terminal of the flip-flop 328 is coupled to receive the "data pulse" signal from the inverter 272 of FIG. 6B. The "transmission valid" signal from the control section 142 of FIG. 4 is coupled to the C, or unconditional clear, input terminal of the flip-flop 328.

When the "transmission valid" signal is at a logic level "0," the flip-flop 328 is in a clear state, and its Q output terminal is at a logic level "0." When the "transmission valid" signal is at a logic level "1," the first logic level "1" "data pulse" signal that is received on the clock input terminal of the flip-flop 328 drives the flip-flop 328 into a set state, and the Q output terminal of the flip-flop 328 is then at a logic level "1." If the output terminal of the inverter 325 is simultaneously at a logic level "1," the output terminal of the NAND-gate 326 will be at a logic level "0." If the "end-of-label reset" signal from the control section 142 of FIG. 4 is at a logic level "1" when the output terminal of the NAND-gate 326 is simultaneously at a logic level "0," the NAND-gate 330 will be driven into a "1" state, the NAND-gate 332 will be driven into a "0" state, and a logic level "1" "end-of-label" signal will be produced on the output terminal of the NAND-gate 330. The generation of the "end-of-label reset" signal will be discussed in more detail subsequently.

The NAND-gate 334 of the memory input synchronization section of FIG. 9 receives the "transmission valid" signal from the control section 142 of FIG. 4 on a first input terminal and the "program counter reset" signal from the inverter 337 of FIG. 10 on a second input terminal. The output terminal of the NAND-gate 334 is coupled to the input terminal of the inverter 336. The output terminal of the inverter 336 is coupled to a first input terminal of the NAND-gate 338, which is cross coupled with the NAND-gate 340 to form a NAND-gate latch circuit, and it is also coupled to the reset input terminal of the A-counter 352. The A-counter 352 is reset when the output signal from the inverter 336 is a logic level "0" "reset A" signal, which occurs either when the "program counter reset" signal is at a logic level "0" or when the "transmission valid" signal is at a logic level "0."

The output terminal of the NAND-gate 340 is coupled to a first input terminal of the NAND-gate 342, which is also coupled to the clock to receive the "clock 3" signal on a second input terminal. The output terminal of the NAND-gate 342 is coupled to the input terminal of the inverter 344, and, therefore, when the "data shift" signal from the NAND-gate 340 is at a logic level "1" and a logic level "1" "clock 3" signal also occurs, the NAND-gate 342 produces a logic level "0" output signal, which is inverted by the inverter 344 to produce a logic level "1" "data shift pulse" output signal, which is supplied to the shift input terminal of the auxiliary memory register 388 of FIG. 11.

The NAND-gate 346 has a first input terminal, coupled to the clock to receive the "clock 1" signal, a second input terminal, coupled to receive the "inhibit strobe" signal from the NAND-gate 350 of FIG. 10, and a third input terminal, coupled to receive the "A=8" signal from the decoding circuitry 354, which is coupled to the A-counter 352. The A-counter 352 is a four-bit counter and counts the number of "shift A" signals that have been produced by the NAND-gate 292 of FIG. 7 when the "data shift" signal is at a logic level "1." The decoding circuitry 354 is a conventional decoding circuit that provides a logic level "1" output signal if the count in the A-counter 352 reaches a count of 8. This signifies that the first bit that entered the input register 280 is positioned in the eighth stage, or the output stage, of the input register 280.

The NAND-gate 346 produces a logic level "0" output signal when a logic level "1" clock "1" signal, a logic level "1" "inhibit strobe" signal, and a logic level "1" "A=8" signal occur simultaneously. When the output terminal of the NAND-gate 346 is at a logic level "0" and the output terminal of the inverter 336 is at a logic level "1," the NAND-gate 340 is driven into a "1" state, and the NAND-gate 338 is driven into a "0" state, thereby producing a logic level "1" "data shift" signal on the output terminal of the NAND-gate 340. The output terminal of the NAND-gate 338 is coupled to a first input terminal of the NAND-gate 356, and a second input terminal of the NAND-gate 356 is coupled to receive the "shift A" signal from the NAND-gate 292 of FIG. 7. When both the "shift A" and the "data shift" signals are simultaneously at a logic level "1," the NAND-gate 356 produces a logic level "0" output signal, and this signal is inverted by the inverter 358 to produce a logic level "1" "increment A" signal, which is coupled to the increment input terminal of the A-counter 352. The A-counter 352 is so constructed that each logic level "1" "increment A" signal that is received on its increment input terminal causes the A-counter 352 to increment its count once. The decoding circuit 360 is a conventional decoding circuit and decodes the A-counter 352 and produces a logic level "1" "A.noteq. 0" output signal if the count in the A-counter 352 is not equal to 0. This signifies that the input register 280 contains at least one data bit. The A-counter 352 and the program counter 400 of FIG. 13 are both coupled to the conventional comparison circuit 362, which produces a logic level "1" "compare A-counter to program counter" signal whenever the counts in those two counters are equal.

The NAND-gate 377 of FIG. 10 has a first input terminal, coupled to the output terminal of the comparison circuit 362, a second input terminal, coupled to the output terminal of the NAND-gate 350 to receive the "inhibit strobe" signal, a third input terminal, coupled to the program counter 400 of FIG. 13 to receive the "program count DEFG" signal, and a fourth input terminal, coupled to the clock to receive the "clock 1" signal. The program counter 400 of FIG. 13 is a seven-bit module counter which can count to 128. The last four stages of the program counter 400 are labeled the DEFG stages, respectively, and the "program count DEFG" signal is a timing signal that is at a logic level "1" whenever the count in the program counter 400 is in the counts 120 through 127. The NAND-gate 377, therefore, produces a logic level "0" output signal when the count in the program counter 400 and the count in the A-counter 352 compare, so as to control the shifting of data into the memory section 130 of FIG. 4 at the proper time in accordance with the number of data bits that are stored in the input register 280.

The NAND-gate 368 and the NAND-gate 370 of FIG. 10 are cross coupled to form a NAND-gate latch circuit. One input terminal of the NAND-gate 368 is coupled to the output terminal of the NAND-gate 377. When the NAND-gate 368 is in a saturated state and the NAND-gate 370 is in a cutoff state, the logic level "0" "fast shift latch" signal that is produced by the NAND-gate 368 is coupled to the reset input terminal of the three-bit counter 378, which can count to a count of "8." A logic level "0" "fast shift latch" signal on the reset input terminal of the counter 378 will reset the counter 378. The output of the NAND-gate 368 is also coupled to a first input terminal of the NAND-gate 366. A second input terminal of the NAND-gate 366 is coupled to the clock to receive the "clock 3" signal. Therefore, when the "fast shift latch" signal is at a logic level "0," the output of the NAND-gate 366 is at a logic level "1."

The flip-flop 380 has its Q output terminal coupled to a first input terminal of the NAND-gate 382, while a second input terminal of the NAND-gate 382 is coupled to the control section 142 to receive the "transmission valid" signal. The flip-flop 380 has both its J and its K input terminals unconnected, and the clock input terminal is coupled to the output stage of the counter 378. The unconditional, or C, input terminal of the flip-flop 380 is coupled to receive the "clock 1" signal from the clock, and, therefore, the flip-flop 380 will remain in a clear state until the "clock 1" signal is at a logic level "1" and the last stage of the counter 378 is at a logic level "1." When the "fast shift latch" signal is at a logic level "0," the counter 378 is reset. The Q output terminal of the flip-flop 380 is at a logic level "1" when the flip-flop 380 is in a clear state, and when the "transmission valid" signal is simultaneously at a logic level "1," the output of the NAND-gate 382 is at a logic level "0," and the output of the inverter 384 is, therefore, at a logic level "1." If the output terminal of the NAND-gate 377 is also at a logic level "0" at the same time, the NAND-gate 370 will be driven into a "0" state, the NAND-gate 368 will be driven into a "1" state, and the "fast shift latch" signal will go to a logic level "1." When the "fast shift latch" signal is at a logic level "1," the "clock 3" signal causes the NAND-gate 366 to produce a logic level "0" output signal each time that a "clock 3" signal is received. After eight "clock 3" signals have been received by the register 378, the output stage of the register 378 will be in a "1" state, and the flip-flop 380 will be driven into a set state. Its Q output terminal will, therefore, go to a logic level "0," causing the output terminal of the inverter 384 to go to a logic level "0" also. A logic level "0" output signal from the NAND-gate 384 resets the counter 374.

The output terminal of the inverter 384 is coupled to the NAND-gate 348, which is cross coupled with the NAND-gate 350 to form a NAND-gate latch circuit. The NAND-gate 348 is in a "0" state and the NAND-gate 350 is in a "1" state when a logic level "1" output signal is supplied by the inverter 384 and a logic level "0" output signal is supplied by the NAND-gate 386. The NAND-gate 386 has a first input terminal, coupled to the program counter section to receive the "program count 120" signal, a second input terminal, coupled to the clock to receive the "clock 1" signal, and a third input terminal, coupled to the decoding circuit of FIG. 9 to receive the "A.noteq.0" signal. Therefore, when the count of the program counter reaches 120, the NAND-gate 386 produces a logic level "0" output signal at "clock 1" time if at least one data bit is stored in the input register 280. The "inhibit strobe" signal will then go to a logic level "1" if the output terminal of the inverter 384 is at a logic level "1."

A first input terminal of the NAND-gate 364 is coupled to the output terminal of the NAND-gate 278 of FIG. 7 to receive the "data strobe" signal, and a second input terminal of the NAND-gate 364 is coupled to the NAND-gate 330 of FIG. 8 to receive the "end-of-label" signal. The output terminals of the NAND-gates 364 and 366 are coupled to input terminals of the NAND-gate 372, and, therefore, the output terminal of the NAND-gate 372 will be at a logic level "1" whenever the output terminal of either the NAND-gate 364 or the NAND-gate 366 is at a logic level "0." The output terminal of the NAND-gate 372 is coupled to the increment input terminal of the three-bit counter 374. The counter 374 increments its count once each time that a logic level "1" output signal is produced by the NAND-gate 372 if the output terminal of the inverter 384 is also at a logic level "1" at this time.

The Q output terminal of the flip-flop 376 is coupled to the input terminal of the inverter 337, which produces the "program counter reset pulse" output signal. Both the J and the K input terminals of the flip-flop 376 are unconnected, and the unconditional clear, or C, input terminal is coupled to the clock to receive the "clock 1" signal. Therefore, the flip-flop 376 remains in a clear state until the last stage of the counter 374 is in a "1" stage. When eight counts of the counter 374 have been completed, the output stage of the counter 374 is in a "1" state, and a logic level "1" output signal from the last stage of the counter 374 is coupled to the clock input terminal of the flip-flop 374, which drives the flip-flop 376 into a set state. When the flip-flop 376 is in a set state, the Q output terminal is at a logic level "1," and the "program counter reset" output signal from the inverter 337 is at a logic level "0," which resets the counter 400 of FIG. 13.

When the "end-of-label" and the "data strobe" signals are both at a logic level "1," the output terminal of the NAND-gate 364 is at a logic level "0." It is possible for an erroneous "end-of-label" signal to be generated as the probe 62 scans portions of a container of an item for sale or a vehicle on which the data-encoded label is placed. A logic level "0" output signal from the NAND-gate 364 indicates that an "end-of-the-label" condition has been sensed by the probe 62 and that the "data strobe" signal is also at a logic level "1." When a valid "end-of-label" signal has been detected, the output terminal of the inverter 384 is at a logic level "0," since the "transmission valid" signal on the input terminal of the NAND-gate 382 is at a logic level "0." The "inhibit strobe" signal from the output terminal of the NAND-gate 348 is then at a logic level "1."

The NAND-gate 364 allows new data to be stored in the input register 280 of FIG. 7 following the detection of an "end-of-label" signal (or an "end-of-media" signal if a data-encoded medium other than a label is employed), so that data is not lost in the event that the "end-of-label" signal that has been generated was not a valid "end-of-label" signal. Data which is received by the input register 280 after the "end-of-label" signal has been generated is recirculated in the input register 280, and it is combined with the previously stored data, and the combined data is checked when a second "end-of-label" signal is generated to determine whether this signal is a valid one.

The first stage of the five-bit auxiliary memory register 132 of FIG. 11 is coupled to receive the "data" and the "data" signals from the output stage of the input register 280 of FIG. 7. The "data shift pulse" signal, which causes data in the auxiliary memory register 132 to be shifted one stage toward the output stage of the register each time that it is received, is coupled to the increment input terminal of the auxiliary memory register 132 from the output terminal of the inverter 344 of FIG. 9. When the auxiliary memory register 132 is full, the last stage of the register 132 will contain a data bit, and, if the data bit is a "1" bit, the logic level "1" signal will be coupled to a first input terminal of the NAND-gate 390. A second input terminal of the NAND-gate 390 is coupled to receive the "data shift" signal from the output terminal of the NAND-gate 340 of FIG. 9. The output of the NAND-gate 390, therefore, is at a logic level "0" when the "data shift" signal is at a logic level "1" and the data bit from the last stage of the register 132 is a "1."

A first input terminal of the NAND-gate 394 is coupled to receive the "data shift" signal from the NAND-gate 338 of FIG. 9, and a second input terminal of the NAND-gate 394 is coupled to the output stage of the memory register 134. When the output stage of the memory register 134 contains a "1" bit, the memory register 134 will supply a logic level "1" output signal to the second input terminal of the NAND-gate 394, and, if the "data shift" signal is also at a logic level "1" at this time, the output of the NAND-gate 394 will be at a logic level "0." A first input terminal of the NAND-gate 392 is coupled to the output terminal of the NAND-gate 390, and a second input terminal of the NAND-gate 392 is coupled to the output terminal of the NAND-gate 394. The output signal from the NAND-gate 392 is controlled by the NAND-gate 390 when new data is to be entered into the memory register 134, and it is controlled by the NAND-gate 394 when data previously stored in the memory register 134 is to be recirculated.

The output of the NAND-gate 392 is coupled to the input terminal of the memory register 134, and a "1" bit will be entered into the memory register 134 each time that the output terminal of the NAND-gate 392 is at a logic level "1." The memory register 134 may be a conventional four-phase metal-oxide-semiconductor shift register or other type of shift register in which data is shifted one stage toward the output stage of the resister each time that a clock phase signal occurs. The memory register 134 may employ conventional signal level converting circuits, if necessary, to convert the signal levels of the input and output signals that are associated with the memory register 134 into logic level signals.

The comparison circuit of FIG. 12 is used for two purposes. It is used first to compare the "size code" bits that are stored in the auxiliary memory register 132 of FIG. 11 with the transposed and inverted count of the last four stages of the program counter 400 of FIG. 13. The program counter 400 of FIG. 13 is a seven-bit module 128 counter; however, this counter can be considered as two counters, a module 8 and a module 16 counter, in which the module 8 counter consists of the first three stages, or the A, B, and C stages, and the module 16 counter consists of the last four stages, or the D, E, F, and G stages. The count in the auxiliary memory register 132 and the count in the module 16 portion of the program counter 400 is compared in order to transfer data from the memory register 134 into the output register 148 of FIG. 4 at the appropriate time.

It may be assumed, for example, that the "size code" is 1011, which corresponds to the code of 11. Each number in the "size code" is considered to represent two digits of data, and, therefore, a "size code" of 1011 represents 22 digits of data of four bits of data per digit of data, or a total of 88 bits of data. In addition, there are 12 bits which are encoded on the label of this example, which include eight "size code" bits, two direction bits, and two parity bits, and, therefore, the total number of bits that are encoded on the label of this example is 100 bits. Of these 100 bits, five bits are stored in the auxiliary memory register 132, and 95 bits are stored in the memory register 134.

In order to bring the first bit of data that would be decoded in this example into the output stage of the memory register 134, the bits that are stored in the memory section 130 must be shifted toward the output stage of the memory register 134 over 128 minus 95, or 33, bit times from the time that the program counter 400 is reset, with all of its stages being driven into a "0" state. Each time that data in the memory section 130 is shifted eight stages toward the output stage of the memory register 134, the module 16 portion of the program counter 400 will increment its count once, and, therefore, after 32 bit times, the count in the module 16 counter portion of the program counter 400 will be 0010.

The count contained in the module 16 counter portion of the program counter 400 is a transposed and inverted representation of the "size code" that is stored in the auxiliary memory register 132. Therefore, by comparing the count that is stored in the D, E, F, and G stages of the program counter with the transposed inverted value of the "size code" bits that are stored in the auxiliary memory register 132, the appropriate time to transfer data from the memory register 134 into the output register 148 is determined. According to the "size code" of this example, the transfer from the memory register 134 into the output register 148 can begin after 33 bit times. The logic that is provided is actually one bit too fast, but no problem is presented if the first bit of data that is transferred is ignored when it is subsequently transferred from the output register 148 to the data utilization device 114 of FIG. 2.

The first five bits of data that are loaded into the output register 148 include the first group of "size code" bits which were sensed and decoded from the label 20. The last five bits that are loaded into the auxiliary memory register 132 include the second group of "size code" bits which were sensed and decoded from the label 20.

The comparison circuit of FIG. 12 then compares the "size code" bits that are stored in the auxiliary memory register 132 with "size code" bits that are stored in the output register 148.

The NAND-gates 101, 103, 105, 107, and 109 of FIG. 12 are coupled to input terminals of the NAND-gate 111, and all of these NAND-gates must produce logic level "1" output signals if the NAND-gate 111 is to produce a logic level "0" output signal. The output of the NAND-gate 111 is coupled to the inverter 113, and, therefore, a logic level "1" "comparison" signal is produced by the inverter 113 only when all of the NAND-gates 101, 103, 105, 107, and 109 produce logic level "1" output signals.

The output terminals of the NAND-gates 115, 117, 119, and 121 are coupled to the input terminals of the NAND-gate 101, and, therefore, if the output terminal of any of these NAND-gates is at a logic level "0," the output terminal of the NAND-gate 101 will be at a logic level "1." The NAND-gate 115 has a first input terminal, coupled to the "false" side of stage B of the auxiliary memory register 132. This input is designated in FIG. 12 as "A. R. stage B," where A. R. represents "auxiliary memory register." The NAND-gate 115 also has a second input terminal, coupled to the "false" side of the G stage of the program counter 400 of FIG. 13. This input is designated as "P. C. stage G," where P. C. represents "program counter." A third input terminal is coupled to the control section 142 of FIG. 4 to receive the "E" signal. The "E" signal is a timing signal which occurs when it is desired to compare the count in the program counter 400 and the "size code" stored in the auxiliary memory register 132.

The NAND-gate 117 has its input terminals coupled to the "true" side of stage B of the auxiliary memory register 132, to the "true" side of stage G of the program counter 400, and to the control section 142 to receive the "E" signal. Therefore, if stage B of the auxiliary memory register 132 and stage G of the program counter 400 are both either in a "O" state or in a "1" state, the output terminal of the NAND-gate 101 may go to a logic level "1." The other bits of the auxiliary memory register 132 and the program counter 400 are compared in a similar manner, as indicated by the corresponding designations on the input terminals of the various NAND-gates of FIG. 12. Therefore, when the "size code" that is contained in the auxiliary memory register 132 and the transposed inverted "size code" count that is contained in the program counter 400 are equal, and a logic level "1" "E" signal is also present, all of the NAND-gates 101, 103, 105, and 107 produce logic level "1" output signals.

The "size code" bits that are stored in the auxiliary memory register 132 are transposed with respect to the "size code" bits that are stored in the output register, 148, because of the manner in which the label 20 is encoded, as previously described. The NAND-gate 119 has its input terminals coupled to the "true" side of stage B of the auxiliary memory register 132 and to the "false" side of the D stage of the output register 142. The signal from the output register 142 is termed the "O. R. stage D" signal, where O. R. represents "output register." The NAND-gate 121 has inputs from the "false" side of stage B of the memory auxiliary register 132 and from the "true" side of stage D of the output register 142. The "F" signal is coupled to input terminals of both the NAND-gates 119 and 121. The "F" signal is a timing signal which occurs when it is desired to compare the "size code" in the auxiliary memory register 132 and the "size code" in the output register 148. Therefore, when the B stage of the auxiliary memory register 132 and the D stage of the output register 148 are both in a "0" state or in a "1" state, the output terminal of the NAND-gate 101 may go to a logic level "1." The other bits of the auxiliary memory register 132 and the output register 148 are compared in a similar manner, as indicated by the corresponding designations on the input terminals of the NAND-gates of FIG. 12. Therefore, when the "size code" that is contained in the auxiliary memory register 132 and the "size code" that is contained in the output register 148 are equal and a logic level "1" "F" signal is also present, all of the NAND-gates 101, 103, 105, and 107 will produce logic level "1" output signals.

The NAND-gate 109 has a first input terminal, coupled to the control section 142 of FIG. 4 to receive the "F" signal, and second and third input terminals, coupled to the output terminals of the NAND-gates 123 and 125. The NAND-gate 123 has its input terminals coupled to the "true" side of the A stage of the auxiliary register 132 and to the "true" side of the E stage of the output register 148. The NAND-gate 125 has its input terminals coupled to the "false" side of the A stage of the auxiliary memory register 132 and to the "false" side of the E stage of the output register 148. The A stage of the auxiliary memory register 132 and the E stage of the output register 148 contain the "direction" bits. It is seen from FIG. 1 that both of the direction bits have the same logical value whether they are a "start" bit or a "stop" bit. Thus, both "direction" bits must be either "1" or "0" bits; therefore, the output of one of the NAND-gates 123 or 125 will be at a logic level "0," and the output of the NAND-gate 121 will be at a logic level "1" when both of the "direction" bits have the same logical value.

When the "direction" bits do not have the same logical value, the output terminals of the NAND-gates 123 and 125 will both be at a logic level "1," and, if the "F" signal is also at a logic level "1," the output terminal of the NAND-gate 109 will be at a logic level "0." A logic level "0" comparison signal is produced by the inverter 113 when the "direction" bits are inconsistent, so that they have opposite logical values. The "direction" bit that is stored in the auxiliary memory register 132 is stored in the A stage of this register, and the code weights of the bits that are stored in the auxiliary memory register 132 increase in code weight through the B, C, D, and E stages, respectively, of this register. The "direction" bit that is stored in the output register 148 is stored in the E stage of this register, and the code weights of the bits that are stored in the output register 148 increase in code weight through the D, C, B, and A stages, respectively, of this register.

The program counter 400 of FIG. 13 has its input terminal coupled to the output terminal of the inverter 404. The inverter 404 has its input terminal coupled to the clock to receive the "clock 3" signal, and, therefore, each time that the inverter 404 produces a logic level "0" output signal, the program counter 400 increments its count. The output of the inverter 337 of FIG. 10 is coupled to the reset input terminal of the program counter 400, and a logic level "0" "program counter reset" pulse output signal from the inverter 337 will reset the program counter 400.

The decoding circuits 406 through 422 (even numbers only) are conventional decoding circuits which decode the counts of the program counter 400 which are shown on their output terminals. A logic level "1" signal is present on the output terminal of the respective decoding circuits 406 through 422 when that particular count occurs in the program counter 400. The decoding circuit 422 decodes the D, E, F, and G stages of the program counter 400 to produce the "program count DEFG" signal, which signifies that all of these stages of the program counter 400 are in a "1" state. The decoding circuits 412, 414, 416, 418, and 420 decode the A, B, and C stages of the program counter 400, and the decoding circuits 406, 408, 410, and 422 decode all of the stages of the program counter 400.

The flip-flops 440 and 442 of FIG. 14 are interconnected to form a conventional module 3 flip-flop counter circuit. The logic level "1" "increment 0" signal which is supplied to the clock input terminals of the flip-flops 440 and 442 and the logic level "0" "reset parity" signal which is supplied to the clear input terminals of the flip-flops 440 and 442 are both derived from the control section 142 of FIG. 4. The flip-flop 440 has a code weight of 1, and the flip-flop 442 has a code weight of 2. The flip-flops 440 and 442 are never in a set state at the same time, since both of the flip-flops 440 and 442 are reset when the count in the counter consisting of the flip-flops 440 and 442 reaches a count of 2. The "preset 0" signal is employed to drive the flip-flop 442 into a set state when a parity check is to be performed and the "size code" contained in the auxiliary memory register 132 and the "size code" contained in the output register 148 are to be compared.

The conventional comparison circuit 448 produces a logic level "1" "parity comparison" signal when the "0" bit count of the flip-flops 440 and 442 is equal to the "1" bit count of the flip-flops 444 and 446. The flip-flops 444 and 446 function in a manner that is analogous to the manner in which the flip-flops 440 and 442 function, and the "increment 1" and the "preset 1" signals are coupled to the flip-flops 444 and 446 instead of the "increment 0" and "preset 0" signals. The flip-flop 442 is preset when the first "direction" bit or the "start" bit that is decoded is a "0" bit, and the flip-flop 446 is preset when the first "direction" bit is a "1" bit.

The complete block diagram of the output register 148 is formed by overlapping FIGS. 15A and 15B along the line 15--15.

The output register 148 of FIGS. 15A and 15B receives data from the memory register 134. Data is always entered into the output register 148 in the order in which they are sensed and decoded. However, since the probe 62 may scan the label in either a left-to-right "forward" direction or in a right-to-left "reverse" direction, the data that is entered into the output register 148, when the probe 62 scans the label 20 in the reverse direction is the complement of the data that is entered into the output register 148 when the probe 62 scans the label 20 in a forward direction. Therefore, when the data is unloaded from the output register 148 into the data utilization device 114 of FIG. 2, it may be shifted from the output register 148 in either a forward direction or in a reverse direction according to the "direction" bits that have been sensed and decoded, since they indicate the direction of the scan of the probe 62.

The output stage of the memory register 134 of FIG. 11, which produces the "memory output" signal, is coupled to a first input terminal of the NAND-gate 424, and the "register forward" signal is coupled from the control section 142 of FIG. 4 to a second input terminal of the NAND-gate 424. When both of the input signals to the NAND-gate 424 are at a logic level "1," the output terminal of the NAND-gate will be at a logic level "0." If the output signal from the memory register 134 is at a logic level "0," the output terminal of the NAND-gate 424 will be at a logic level "1." The NAND-gate 426 has a first input terminal, coupled to the control section 142 to receive the "register reverse" signal, which is at a logic level "0" when the "register forward" signal is at a logic level "1," and therefore the output terminal of the NAND-gate 426 is at a logic level "1" when the "register reverse" signal is at a logic level "0." The output terminals of the NAND-gates 424 and 426 are coupled to the input terminals of the NAND-gate 428, and the output terminal of the NAND-gate 428 will, therefore, be at a logic level "0" whenever the output terminal of the NAND-gate 424 is at a logic level "1." Thus a "0" output signal from the memory register 134 will produce a logic level "0" output signal from the NAND-gate 428, and a "1" output signal from the memory register 134 will produce a logic level "1" output signal from the NAND-gate 428, when data is being loaded into the output register 148.

The inverter 430 is coupled to the output terminal of the NAND-gate 428, and the output terminal of the inverter 430 is coupled to the K input terminal of the inverter input stage flip-flop 432, while the output terminal of the NAND-gate 428 is coupled to the J input terminal of the input stage flip-flop 432. The clock input terminal of the flip-flop 432 is coupled to the control section 142 to receive the "register clock" signal, and, therefore, whenever a logic level "0" output signal is coupled from the memory register 134 to the first input terminal NAND-gate 424 and a logic level "1" "register clock" signal is simultaneously present on the clock input terminal of the flip-flop 432, the flip-flop 432 will be driven into a clear state. On the other hand, if a logic level "1" output signal is produced by the memory register 134, the output terminal of the NAND-gate 428 will be at a logic level "1," and the appearance of a logic level "1" "register clock" signal on the clock input terminal of the flip-flop 432 will cause the flip-flop 432 to be driven into a set state. The Q output terminal of the flip-flop 432, therefore, will be at a logic level "1" or at a logic level "0" according to whether or not the output stage of the memory register 134 is in a "1" state or in a "0" state.

The remaining seven stages of the output register 148 have input circuits which are similar to the input circuit formed by the NAND-gate 424, 426, and 428 and the inverter 430, which are interconnected to form a conventional shift register in which each data bit that is entered into the input stage flip-flop 432 is shifted toward the output stage flip-flop 440. The output stage of the shift register does not have an associated NAND-gate which is connected to receive the "register reverse" signal, since data is entered into the output register 148 only in the "forward" direction.

The NAND-gate 434 of FIG. 15B has a first input terminal, coupled to the Q output terminal of the output stage flip-flop 440, and a second input terminal, coupled to receive the "register forward" signal. The NAND-gate 436 has a first input terminal, coupled to the Q output terminal of the input stage flip-flop 432, and a second input terminal, coupled to receive the "register reverse" signal. The output terminals of the NAND-gates 434 and 436 are both coupled to input terminals of the NAND-gate 438. Therefore, when the output terminal of either the NAND-gate 434 or the NAND-gate 436 is at a logic level "0," the output terminal of the NAND-gate 438 is at a logic level "1," and this "data output" signal is coupled to the data utilization device 114 of FIG. 2.

When the "register forward" signal is at a logic level "1" and the "register reverse" signal is at a logic level "0" and data is to be coupled from the output register 148 to the data utilization device 114, data bits are shifted from the input stage flip-flop 432 toward the output stage flip-flop 440. The "1" and the "0" data bits which are stored in the flip-flop 440 will determine the output state of the NAND-gate 434, and consequently they will also determine whether the NAND-gate 438 will produce a logic level "1" or a logic level "0" "data output" signal. If the scanning probe 62 has traversed the label 20 in the reverse direction and data is to be transposed from the output register 148 to the data utilization device 114, the "register reverse" signal will be at a logic level "1," and the "register forward" signal will be at a logic level "0," and data that is stored in the output register 148 will be shifted from the output stage flip-flop 440 toward the input stage flip-flop 432. In this instance, the state of the Q output of the flip-flop 432 will determine the output stage of the NAND-gate 436, and consequently it will also determine whether the NAND-Gate 438 will produce a logic level "1" or a logic level "0" "data output" signal. The Q output of the flip-flop 432 is selected because the data must be complemented when a reverse direction reading of the label 20 occurs.

The NAND-gate 502 of FIG. 16 is coupled to the inverter 337 of FIG. 10 to receive the "program counter reset" signal and to the NAND-gate 330 of FIG. 8 to receive the "end-of-label" signal. When the "program counter reset" signal and the "end-of-label" signal are simultaneously at a logic level "1," the NAND-gate 502 will produce a logic level "0" "reset parity" output signal. The NAND-gate 504 is coupled to the output terminal of the decoding circuit 416 of FIG. 13 to receive the "program count 7" signal and to the output terminal of the inverter 113 of FIG. 12 to receive the "comparison" signal. The output terminal of the NAND-gate 504 will initially be at a logic level "1," since the "comparison" signal from the inverter 113 is at a logic level "0" unless either the "E" or the "F" signals from the control section 142 of FIG. 4 are at a logic level "1" and the desired comparison is obtained. The "E" signal goes to a logic level "1" before the "F" signal goes to a logic level "1," and, when the "E" signal is at a logic level "1," the comparison circuit of FIG. 12 compares the bits stored in the auxiliary memory register 132 and the count in the program counter 400 to control the transfer of data from the memory register 134 into the output register 148 in the manner previously described.

The NAND-gate 506 is cross coupled with the NAND-gate 508 to form a NAND-gate latch circuit. The NAND-gate 506 has an input terminal coupled to the output terminal of the NAND-gate 502. The NAND-gate 508 has a first input terminal, coupled to the output terminal of the NAND-gate 504, and a second input terminal, coupled to the output terminal of the inverter 510 of FIG. 17, which produces the "transmission valid" signal. The "transmission valid" signal is initially at a logic level "1," and the output terminal of the NAND-gate 504 will initially be at a logic level "1" also, since the "comparison" signal is at a logic level "0" at this time. Therefore, if the output of the NAND-gate 502 is simultaneously at a logic level "0," the parity counter flip-flops 440, 442, 444, and 446 of FIG. 14 will be reset, and the NAND-gate 508 will be driven into a "0" state, while the NAND-gate 506 will be driven into a "1" state, and the "E" output signal from the NAND-gate 506 will be at a logic level "1."

When the "transmission valid" signal goes to a logic level "0," the data that has been sensed and decoded has been verified as valid data. Upon the simultaneous occurrence of a logic level "1" "comparison" signal and a logic level "1" "program count 7" signal, the output terminal of the NAND-gate 504 will also be at a logic level "0," and, if the "program counter reset" signal is simultaneously at a logic level "0," the output terminal of the NAND-gate 502 will be at a logic level "1," and, therefore, the NAND-gate 506 will be driven into a "0" state, the NAND-gate 508 will be driven into a "1" state, and the "E" signal will return to a logic level "0."

The output terminal of the NAND-gate 506 is coupled to a first input terminal of the NAND-gate 512, a second input terminal of the NAND-gate 512 is coupled to the output terminal of the inverter 113 of FIG. 12 to receive the "comparison" signal, and a third input terminal is coupled to the output terminal of the decoding circuit 416 of FIG. 13 to receive the "program count 6" signal. Therefore, when the count in the program counter 400 is at a count of 6, the "E" signal is at a logic level "1," and the "comparison" signal is at a logic level "1," the NAND-gate 512 will produce a logic level "0" output signal.

The NAND-gate 514 is cross coupled with the NAND-gate 516 to form a NAND-gate latch circuit, and the NAND-gate 516 has an input terminal coupled to the output terminal of the decoding circuit 406 of FIG. 13 to receive the "program counter 000" signal. Therefore, when the program counter 400 is not reset, a logic level "1" signal will be supplied to the input terminal of the NAND-gate 516 from the decoding circuit 406 at "clock 3" time. A logic level "0" signal will be supplied to the input terminal of the NAND-gate 514 from the output terminal of the NAND-gate 512 when the "E" signal and the "comparison" signal are simultaneously at a logic level "1" and the count in the program counter 400 is at a count of 6. The NAND-gate 516 will then be driven into a "0" state and the NAND-gate 514 will be driven into a "1" state, producing a logic level "1" "parity latch" signal on the output terminal of the NAND-gate 514.

The output terminal of the NAND-gate 514 is coupled to a first input terminal of both of the NAND-gates 518 and 520, and the second input terminal of both of the NAND-gates 518 and 520 are coupled to the clock to receive the "clock 1" signal. A third input terminal on the NAND-gate 518 is coupled to the output terminal of the inverter 522, and a third input terminal of the NAND-gate 520 is coupled to the output terminal of the decoding circuit 412 of FIG. 13, to receive the "program count 1" signal. The "parity latch" output signal from the NAND-gate 514 will remain at a logic level "1" until the "program count 000" signal is at a logic level "0" and the output terminal of the NAND-gate 512 is simultaneously at a logic level "1."

The NAND-gate 524 is cross coupled with the NAND-gate 526 to form a NAND-gate latch circuit. An input terminal of the NAND-gate 524 is coupled to the output terminal of the NAND-gate 534, and an input terminal of the NAND-gate 526 is coupled to the data utilization device of FIG. 2 to receive the "general reset" signal. The NAND-gate 524 is initially in a "0" state, and the NAND-gate 526 is initially in a "1" state, before a label is read. Therefore, the NAND-gate 526 initially produces a logic level "1" "encode compare" signal, and the NAND-gate 524 initially produces a logic level "0" "encode compare" signal. The output terminal of the NAND-gate 526 is coupled to a first input terminal of the NAND-gate 528, and a second input terminal of the NAND-gate 528 is coupled to the decoding circuit 418 of FIG. 13, to receive the "program count 0" signal. Upon the occurrence of a logic level "1" "program count 0" signal, the NAND-gate 528 will produce a logic level "0" output signal, which will be inverted by the inverter 522, and a logic level "1" signal will be supplied to the second input terminal of the NAND-gate 518. When all of the input terminals of the NAND-gate 518 are at a logic level "1," the output terminal of the NAND-gate 518 will be at a logic level "0." Since the "program count 1" signal that is supplied to the input terminal of the NAND-gate 520 is at a logic level "0" when the "program count O" signal that is supplied to the input terminal of the NAND-gate 528 is at a logic level "1," the output terminal of the NAND-gate 520 will be at a logic level "1" at this time.

The NAND-gate 530 is cross coupled with the NAND-gate 532 to form a NAND-gate latch circuit. A first input terminal of the NAND-gate 532 is coupled to the output terminal of the NAND-gate 530, and a second input terminal of the NAND-gate 532 is coupled to the output terminal of the NAND-gate 520. The output terminal of the inverter 510 of FIG. 17 is also coupled to a third input terminal of the NAND-gate 532 to supply the "transmission valid" signal to the NAND-gate 532. The NAND-gate 532 will, therefore, be driven into a "0" state whenever the "transmission valid" signal is at a logic level "1," the output terminal of the NAND-gate 520 is at a logic level "1," and the output terminal of the NAND-gate 530 is at a logic level "0." When the NAND-gate 532 is driven into a "0" and the NAND-gate 530 is driven into a "1" state, the NAND-gate 530 produces a logic level "1" "F" output signal.

The NAND-gate 534 has a first input terminal, coupled to the output terminal of the inverter 113 of FIG. 12 to receive the "comparison" signal from the inverter 113, which indicates that the value of the "size code" that is contained in the auxiliary memory register 132 is equal to the value of the "size code" which is contained in the output register 148 when the "F" signal is at a logic level "1." A second input terminal of the NAND-gate 534 is coupled to the clock to receive the "clock 3" signal, and the third input terminal of the NAND-gate 534 is coupled to the output terminal of the NAND-gate 530 to receive the "F" signal. When all of the input signals to the NAND-gate 534 are at a logic level, "1," the output signal of the NAND-gate 534 will be at a logic level "0." The "general reset" signal from the data utilization device 114 of FIG. 2, which is coupled to an input terminal of the NAND-gate 526, is initially at a logic level "1," and, therefore, the NAND-gate 526 will be driven into a "0" state, and the NAND-gate 524 will be driven into a "1" state, and the "encode compare" signal will go to a logic level "0," while the "encode compare" signal will go to a logic level "1."

The output terminal of the NAND-gate 524 is coupled to a first input terminal of the NAND-gate 527, and a second input terminal of the NAND-gate 527 is coupled to receive the "parity comparison" signal from the comparison circuit 448 of FIG. 14. When both of the input signals to the NAND-gate 527 are at a logic level "1," the NAND-gate 527 will produce a logic level "0" "data incorrect" signal, which is inverted by the inverter 531 to produce a logic level "1" "data correct" signal.

The NAND-gate 533 has a first input terminal, coupled to the output terminal of the inverter 531, a second input terminal, coupled to the output terminal of the NAND-gate 514, a third input terminal, coupled to the output terminal of the decoding circuit 408 of FIG. 13 to receive the "program count 127" signal, and a fourth input terminal, coupled to the clock to receive the "clock 3" signal. Therefore, when the inverter 531 produces a logic level "1" output signal, a logic level "0" output signal will be produced by the NAND-gate 533 at the appropriate time if the "parity latch" signal is at a logic level "1," and this output signal, which is termed the "correct data pulse" signal, is coupled to the input terminal of the NAND-gate 535 of FIG. 17.

The NAND-gate 535 and the NAND-gate 536 of FIG. 17 are cross coupled to form a NAND-gate latch circuit. An input terminal of the NAND-gate 536 is coupled to receive the "general reset" signal from the data utilization device 114, and, if the "general reset" signal is at a logic level "1," the NAND-gate 536 will be driven into a "0" state, and the NAND-gate 535 is driven into a "1" state when the "data correct pulse" signal is simultaneously at a logic level "0," and the NAND-gate 535 then produces a logic level "1" "data correct latch" signal. The output terminal of the NAND-gate 536 is coupled to a first input terminal of the NAND-gate 538, and the second input terminal of the NAND-gate 538 is coupled to the Q output terminal of the flip-flop 546. When the output terminal of the NAND-gate 536 is at a logic level "0," the output terminal of the NAND-gate 538 is at a logic level "1," and the inverter 510, therefore, will produce a logic level "0" "transmission valid" signal when the data sensed from the label 20 is valid data. This signal prevents new data from being read into the memory section 130 until the data that is already stored there is transferred to the data utilization device 114 of FIG. 2.

The flip-flop 546 of FIG. 17 has its K input terminal coupled to an earth potential and its J input terminal coupled to receive the "black pulse" signal from the decoding section 126 of FIG. 4. The unconditional, or C, input terminal of the flip-flop 546 is coupled to receive the "white pulse" signal from the decoding section 126. The clock input terminal of the flip-flop 546 is coupled to the inverter 312 of FIG. 8 to receive the "end-of-transmission" signal. Thus, whenever the first white colored bar is sensed, a logic level "0" "white pulse" signal will be provided to the C input terminal of the flip-flop 546, and the flip-flop 546 will be driven into a clear state. When the probe 62 is removed from the label 20 which is being scanned, a logic level "1" "black pulse" signal is produced, which is supplied to the J input terminal of the flip-flop 546, and the simultaneous occurrence of the logic level "1" "end-of-transmission" signal on the clock input terminal of the flip-flop 546 will drive the flip-flop 546 into a set state. When the flip-flop 546 is in a set state, the Q output terminal of the flip-flop 546 is at a logic level "0," the output terminal of the NAND-gate 538 is at a logic level "1," and the inverter 510, therefore, produces a logic level "0" "transmission valid" signal.

The NAND-gate 542 of FIG. 16 has a first input terminal, coupled to the output terminal of the decoding circuit 408 of FIG. 13 to receive the "program count 127" signal, a second input terminal, coupled to the clock to receive the "clock 3" signal, a third input terminal, coupled to the output terminal of the NAND-gate 514 to receive the "parity latch" signal, and a fourth input terminal, coupled to the output terminal of the NAND-gate 527 to receive the "data incorrect" signal. When the "data incorrect" signal is at a logic level "0," the output terminal of the NAND-gate 542 will be at a logic level "1," and, since the "transmission valid" signal is initially at a logic level "1," the NAND-gate 540 will produce a logic level "0" output signal when valid data has been sensed and decoded from the label 20. The output terminal of the NAND-gate 540 is coupled to the input terminal of the inverter 544, which produces a logic level "1" "end-of-label reset" signal. When the output terminal of the NAND-gate 542 is at a logic level "0" and the "transmission valid" signal is simultaneously at a logic level "1," the "end-of-label reset" signal is at a logic level "0," which means that the "end-of-label" signal that was generated was an erroneous signal. The "end-of-label reset" signal is coupled to an input terminal of the NAND-gate 332 of FIG. 8.

The output terminal of the NAND-gate 526 is coupled to the input terminal of the inverter 548, and the output terminal of the inverter 548 is coupled to a first input terminal of the NAND-gate 550. A second input terminal of the NAND-gate 550 is coupled to the input stage of the auxiliary memory register 132 of FIG. 11 to receive the "direction" bit. The "direction" bit is the first and last bits read from the label 20. Thus, the first stage of the auxiliary memory register 132 will contain the direction bit after all bits have been transferred from the input register section 128 in FIG. 4. If the "direction" bit signal is a logic level "0," a forward direction read is indicated, and, if the "direction" bit signal is a logic level "1, " a reverse direction read is indicated.

Therefore, when the output terminal of the NAND-gate 526 is at a logic level "0," the output terminal of the inverter 548 will be at a logic level "1." Then, if the "direction" bit is a "1" bit and the output terminal of the NAND-gate 550 is at a logic level "0," and if the "direction" bit is a "0" bit, the output terminal of the NAND-gate 550 will be at a logic level "1."

The NAND-gate 552 is cross coupled with the NAND-gate 554 to form a NAND-gate latch circuit. The NAND-gate 552 has an input terminal coupled to the output terminal of the NAND-gate 550, and a first input terminal of the NAND-gate 554 is coupled to receive the "general reset" signal from the data utilization device 114 of FIG. 2. Thus, when the "direction" bit is a "1" bit and the "general reset" signal from the input of the NAND-gate 554 is simultaneously at a logic level "1," the NAND-gate 554 will be driven into a saturated state, and the NAND-gate 552 will be driven into a cutoff state. When the NAND-gate 552 is in a "1" state, it produces a logic level "1" "reverse latch" signal, and the NAND-gate 554 produces a logic level "0" "reverse latch" signal. If the "direction" bit is a "0" bit, the NAND-gate 552 will remain in a "0" state, and the NAND-gate 554 will remain in a "1" state, and, therefore, a logic level "0" "reverse latch" signal will be produced and appear by the NAND-gate 552, and a logic level "1" "reverse latch" signal will be produced by the NAND-gate 554 in this case.

The input terminal of the inverter 556 of FIG. 17 is coupled to the auxiliary memory register 132 of FIG. 11 to receive the first "direction" bit. The NAND-gate 558 has a first input terminal, coupled to the output terminal of the inverter 556, a second input terminal, coupled to the output terminal of the inverter 113 of FIG. 12 to receive the "comparison" signal, which represents a comparison of the count of the program counter 400 and the bits stored in the auxiliary memory register 132, a third input terminal, coupled to the decoding circuit 412 of FIG. 13 to receive the "program count 1" signal, and a fourth input terminal, coupled to the output terminal of the NAND-gate 506 to receive the "E" signal. Thus, when the count of the D, E, F, and G stages of the program counter 400 and the bits stored in the auxiliary memory register 132 are equal, and the "direction" bit is a "0" bit, the NAND-gate 558 will produce a logic level "0" "preset 0" output signal.

The NAND-gate 560 has a first input terminal, coupled to the auxiliary memory register 132 to receive the "direction" bit, and the other three input terminals of the NAND-gate 560 receive the same input signals as the NAND-gate 558. Therefore, when the "direction" bit is a "1" bit, the NAND-gate 560 will produce a logic level "1" "preset 1" output signal. When the "direction" bit is a "1," the NAND-gate 560 will produce a logic level "0" "preset 1" signal. The "preset 1" and "preset 0" signals are coupled to preset input terminals of the flip-flops 442 and 446, which are employed to check the parity of the data stored in the memory section 130, as previously described.

The input terminal of the inverter 562 is coupled to the output stage of the memory register 134 of FIG. 11 to receive data from the memory register 134. The NAND-gate 566 has a first input terminal, coupled to the output terminal of the inverter 562, a second input terminal, coupled to the clock to receive the "clock 1" signal, and a third input terminal, coupled to the output terminal of the NAND-gate 514 of FIG. 16 to receive the "parity latch" signal. The NAND-gate 564 has a first input terminal, coupled to the output stage of the memory register 134, a second input terminal, coupled to the clock to receive the "clock 1" signal, and a third input terminal, coupled to the output terminal of the NAND-gate 514 to receive the "parity latch" signal.

When the output stage of the memory register 134 contains a "0" bit, the output terminal of the NAND-gate 564 will go to a logic level "1," and the output terminal of the NAND-gate 566 will go to a logic level "0" at "clock 1" time if the "parity latch" signal is at a logic level "1." When the output stage of the memory register 134 contains a "1" bit, the output terminal of the NAND-gate 564 will go to a logic level "0," and the output terminal of the NAND-gate 566 will go to a logic level "1." The input terminal of the inverter 568 is coupled to the output terminal of the NAND-gate 564, and it inverts the output signal from the NAND-gate 564 to produce the "increment 1" signal. The input terminal of the inverter 570 is coupled to the output terminal of the NAND-gate 566, and it inverts the output signal from the NAND-gate 566 to produce the "increment 0" signal. The output terminal of the inverter 568 is coupled to the clock input terminal of the flip-flops 444 and 446, and the output terminal of the inverter 570 is coupled to the clock input terminals of the flip-flops 440 and 442.

A first input terminal of the NAND-gate 572 is coupled to the output terminal decoding circuit 420 of FIG. 13 to receive the "program count 0-5" signal, which signifies that the count of the A, B, and C stages of the program counter 400 400 are in a count from 0 to 5. A second input terminal of the NAND-gate 572 is coupled to the output terminal of the inverter 113 of FIG. 12 to receive the "comparison" signal, which in this instance is at a logic level "1" when the count in the D, E, F, and G stages of the program counter 400 and the bits stored in the auxiliary memory register 132 are equal. The third input terminal of the NAND-gate 572 is coupled to receive the "E" signal from the output terminal of the NAND-gate 506 of FIG. 16. Therefore, the output terminal of the NAND-gate 572 is at a logic level "0" when the "program count 0-5" signal is at a logic level "1," and a comparison is made between the count in the D, E, F, and G stages of the program counter 400, and the bits stored in the auxiliary memory register 132, which provides for the transfer of the "size code" bits from the memory register 134 into the output register 148. The output terminal of the NAND-gate 572 is coupled to the input terminal of the NAND-gate 574, which produces the "register forward" signal.

The NAND-gate 573 receives the "register load" command signal from the data utilization device 114 on a first input terminal, and a second input terminal of the NAND-gate 573 is coupled to the output terminal of the NAND-gate 533 of FIG. 16 to receive the "data correct latch" signal. The output terminal of the NAND-gate 573 will, therefore, be at a logic level "0," and the NAND-gate 574 will produce a logic level "1" "register forward" signal whenever both of the input signals to the NAND-gate 573 are at a logic level "1." In this manner, data stored in the memory register 134 is transferred into the output register 148.

The NAND-gate 576 has a first input terminal, coupled to the NAND-gate 554 of FIG. 16 to receive the "reverse latch" signal, a second input terminal, coupled to the data utilization device 114 of FIG. 2 to receive the "transmit" command signal from the data utilization device 114, and a third input terminal, coupled to the output terminal of the NAND-gate 535 to receive the "data correct latch" signal. When the output register 148 has been correctly loaded with data, the data utilization device 114 will supply a logic level "1" "transmit" signal to the NAND-gate 576. When the "direction" bit is a "0" bit and the "reverse latch" signal is at a logic level "1," and the output terminal of the NAND-gate 576 will be at a logic level "0," and the output terminal of the NAND-gate 574 will, therefore, be at a logic level "1," The NAND-gate 578 has a first input terminal, coupled to the output terminal of the NAND-gate 552 to receive the "reverse latch" signal, a second input terminal, coupled to the data utilization device 114 to receive the "transmit" signal, and a third input terminal, coupled to the output terminal of the NAND-gate 535 to receive the "data correct latch" signal. The output terminal of the NAND-gate 578 is coupled to the input terminal of the inverter 580, and, therefore, whenever the input signals to the NAND-gate 578 are all at a logic level "1," the inverter 580 will produce a logic level "1" "register reverse" signal.

When a logic level "1" "register forward" signal is produced and the "transmit" and "data correct latch" signals are also at a logic level "1," the data bits that are stored in the output register 148 will be shifted from the input stage toward the output stage of the output register 148. When the "register reverse" signal is at a logic level "1" and the "transmit" signal and the "data correct latch" signal are also at a logic level "1," the data bits that are stored in the output register 148 will be shifted from the output stage to the input stage of the output register 148. Thus, the data is always stored in the output register 148 in a left-to-right direction, regardless of the direction of scan of the probe 62 across the label 20, but data is read out of the output register 148 in either a left-to-right direction or a right-to-left direction, according to the direction of scan of the probe 62 across the label 20.

The NAND-gate 582 has a first input terminal, coupled to the output terminal of the NAND-gate 574, and a second input terminal, coupled to the clock to receive the "clock 1" signal. The NAND-gate 584 has a first input terminal, coupled to the output terminal of the inverter 580, and a second input terminal, coupled to the clock to receive the "clock 1" signal. The NAND-gate 586 has a first input terminal, coupled to the output terminal of the NAND-gate 582, and a second input terminal, coupled to the output terminal of the NAND-gate 584. Therefore, when either of the NAND-gates 582 or 584 have input signals on both of their respective input terminals which are set at a logic level "1," the output terminal of the NAND-gate will be at a logic level "0," and the output terminal of the NAND-gate 586 will then be at a logic level "1." The output terminal of the NAND-gate 586 is termed the "register clock" signal, and it is coupled to the clock input terminals of the flip-flops of the output register 148 of FIGS. 15A and 15B.

Claims

What is claimed is:

1. An identification system comprising:

a. a data-encoded medium that comprises a plurality of data indicia wherein each data indicium is selected from a group of three or more data indicia, and each data indicium is different from its neighboring data indicia, and

b. means to sense data indicia in pairs as a transition of the sensing means across a first data indicium of the pair to a second data indicium of the pair occurs, and

c. means coupled to the sensing means that is constructed to remember the first data indicium of the pair until the second data indicium of the pair is sensed, and to generate a signal that is representative of the associated binary bit based on the particular first and the second data indicia which were sensed.

2. An identification and validation system comprising:

a. a data-encoded medium that includes a plurality of data indicia wherein each data indicium is selected from a group of three or more data indicia, and each data indicium is different from its neighboring data indicia,

b. means to sense data indicia in pairs as a transition of the sensing means across a first data indicium of the pair to a second data indicium of the pair occurs, and

c. means coupled to the sensing means that is constructed to remember the first data indicium of the pair until the second data indicium of the pair is sensed, and to generate a signal that is representative of an associated binary bit based on the particular first and second data indicia which were sensed,

wherein a first group of size code binary bits are sensed first, the value of the first group of size code bits being representative of the number of data binary bits that are encoded on the medium, the data bits are sensed second, and a second group of size code binary bits are sensed third, the recorded values of the first and second groups of size code bits on the data-encoded medium being equal, said system further including:

d. memory means coupled to receive the bits that are sensed from a data-encoded medium that is constructed to store all of the binary bits sensed from the medium, and

e. means constructed to produce an end-of-medium signal after the last recorded binary bit of the medium has been sensed by the sensing means, and

f. validation means coupled to the memory means and to the end-of-medium signal producing means that is constructed to signify that a properly encoded medium has been correctly sensed when the end-of-medium signal is produced and the first and second groups of size code bits that are stored in the memory means are equal.

3. A validation system for an identification system as in claim 2 wherein:

a. a first parity bit and a second parity bit are sensed from the encoded medium and are stored in the memory means, and

b. means are coupled to the memory means and to the validation means that are constructed to couple a parity check signal to the validation means when the first and second parity bits and the data bits that are stored in the memory means correspond to a predetermined parity standard, the validation means being constructed so that it will not signify that a properly encoded medium has been correctly sensed until the parity check signal is generated.

4. An identification system comprising:

a. a data-encoded medium that includes a plurality of data indicia wherein each data indicium is selected from a group of three or more indicia, and each data indicium is different from its neighboring data indicia,

b. means to sense data indicia in pairs as a transition of the sensing means across a first data indicium of the pair to a second data indicium of the pair occurs, and

c. means coupled to the sensing means that is constructed to remember the first data indicium of the pair until the second data indicium of the pair is sensed, and to generate a signal that is representative of the associated binary bit based on the particular first and second data indicia which were sensed,

d. wherein a portion of the sensed binary bits indicate whether the transition of the sensing means across the data indicia was in the normal forward direction or whether it was in the opposite, or reverse, direction, and

e. wherein the means coupled to the sensing means is so constructed that the signal that is representative of the associated binary bit is, in addition, based on the direction of transition of the sensing means across the data indicia.

5. A validation system for an identification system as in claim 4 wherein a first group of size code binary bits are sensed first, the value of the first group of size code bits being representative of the number of data binary bits that are encoded on the medium, the data bits are sensed second, and a second group of size code binary bits are sensed third, the recorded values of the first and second groups of size code bits on the data-encoded medium being equal, comprising:

a. memory means coupled to receive the bits that are sensed from a data-encoded medium that is constructed to store all of the binary bits sensed from the medium, and

b. means constructed to produce an end-of-medium signal after the last recorded binary bit of the medium has been sensed by the sensing means, and

c. validation means coupled to the memory means and to the end-of-medium signal producing means that is constructed to signify that a properly encoded medium has been correctly sensed when the end-of-medium signal is produced and the first and second groups of size code bits that are stored in the memory means are equal.

6. A validation system for an identification system as in claim 5 wherein:

a. a first parity bit and a second parity bit are sensed from the encoded medium and are stored in the memory means, and

b. means are coupled to the memory means and to the validation means that are constructed to couple a parity check signal to the validation means when the first and second parity bits and the data bits that are stored in the memory means correspond to a predetermined parity standard, the validation means being so constructed that it will not signify that a properly encoded medium has been correctly sensed until the parity check signal is generated.

7. An identification system comprising:

a. a data-encoded medium that includes a plurality of data indicia wherein each data indicium is selected from a group of three of more indicia, and each data indicium is different from its neighboring data indicia,

b. means to sense data indicia in pairs as a transition of the sensing means across a first data indicium of the pair to a second data indicium of the pair occurs, and

c. means coupled to the sensing means that is constructed to remember the first data indicium of the pair until the second data indicium of the pair is sensed, and to generate a signal that is representative of the associated binary bit based on the particular first and second data indicia which were sensed,

d. wherein the data indicia consists of a plurality of contiguous colored bars, each colored bar being of a first, a second, or a third color, and each colored bar being of a color different from the color of its neighboring colored bars, and

e. the sensing means includes

1. means to direct a light spot onto the medium, and

2. means to guide reflected light signal from the medium, and

3. signal-splitting means which are coupled to receive the reflected signals that are guided from the medium by the guide means of the sensing means, the signal-splitting means being constructed to produce a first light-signal component, which is substantially reflected from both the first and the second colors of the colored bars of the medium, and a second light-signal component, which is substantially reflected from only the first color of the colored bars of the medium, neither the first nor the second light-signal components being substantially reflected from the third color of the colored bars of the medium, and

f. wherein the means coupled to the sensing means includes

1. means which are constructed to receive the first and the second light-signal components and to produce three signals, each of the signals being representative of one of the colors of the colored bars of the medium, and

2. means constructed to remember the signal that is associated with a first color bar until a signal that is associated with a second colored bar is produced, and to generate a signal that is representative of the associated binary bit based upon the particular first and second colored bars which were sensed.

8. A validation system for an identification system as in claim 7 wherein a first group of size code binary bits are sensed first, the value of the first group of size code bits being representative of the number of data binary bits that are encoded on the medium, the data bits are sensed second, and a second group of size code binary bits are sensed third, the recorded values of the first and second groups of size code bits on the data-encoded medium being equal, comprising:

a. memory means coupled to receive the bits that are sensed from a data-encoded medium that is constructed to store all of the binary bits sensed from the medium, and

b. means constructed to produce an end-of-medium signal after the last recorded binary bit of the medium has been sensed by the sensing means, and

c. validation means coupled to the memory means and to the end-of-medium signal producing means that is constructed to signify that a properly encoded medium has been correctly sensed when the end-of-medium signal is produced and the first and second groups of size code bits that are stored in the memory means are equal.

9. A validation system for an identification system as in claim 8 wherein:

a. a first parity bit and a second parity bit are sensed from the encoded medium and are stored in the memory means, and

b. means are coupled to the memory means and to the validation means that are constructed to couple a parity check signal to the validation means when the first and second parity bits and the data bits that are stored in the memory means correspond to a predetermined parity standard, the validation means being so constructed that it will not signify that a properly encoded medium has been correctly sensed until the parity check signal is generated.

10. An identification system as in claim 7 wherein:

a. a portion of the sensed binary bits indicate whether the transition of the sensing means across the data indicia was in the normal forward direction or whether it was in the opposite, or reverse, direction, and

b. the means coupled to the sensing means is so constructed that the signal that is representative of the associated binary bit is, in addition, based on the direction of transition of the sensing means across the data indicia.

11. A validation system for an identification system as in claim 10 wherein a first group of size code binary bits are sensed first, the value of the first group of size code bits being representative of the number of data binary bits that are encoded on the medium, the data bits are sensed second, and a second group of size code binary bits are sensed third, the recorded values of the first and second groups of the size code bits on the data-encoded medium being equal, comprising:

a. memory means coupled to receive the bits that are sensed from a data-encoded medium that is constructed to store all of the binary bits sensed from the medium, and

b. means constructed to produce an end-of-medium signal after the last recorded binary bit of the medium has been sensed by the sensing means, and

c. validation means coupled to the memory means and to the end-of-medium signal producing means that is constructed to signify that a properly encoded medium has been correctly sensed when the end-of-medium signal is produced and the first and second groups of size code bits that are stored in the memory means are equal.

12. A validation system for an identification system as in claim 11 wherein:

a. a first parity bit and a second parity bit are sensed from the encoded medium and are stored in the memory means, and

b. means are coupled to the memory means and to the validation means that are constructed to couple a parity check signal to the validation means when the first and second parity bits and the data bits that are stored in the memory means correspond to a predetermined parity standard, the validation means being so constructed that it will not signify that a properly encoded medium has been correctly sensed until the parity check signal is generated.

13. A validation system for an identification system comprising:

a. means to sense data indicia that are recorded on a data-encoded medium, wherein a first group of size code binary bits are sensed first, the value of the first group of size code bits being representative of the number of data binary bits that are encoded on the medium, the data bits are sensed second, and a second group of size code binary bits are sensed third, the recorded values of the first and second groups of size code bits on the data-encoded medium being equal, and

b. memory means coupled to receive the data bits that are sensed from a data-encoded medium that is constructed to store all of the binary bits sensed from the medium, and

c. means constructed to produce an end-of-medium signal after the last recorded binary bit of the medium has been sensed by the sensing means, and

d. validation means coupled to the memory means and to the end-of-medium signal producing means that is constructed to signify that a properly encoded medium has been correctly sensed when the end-of-medium signal is produced and the first and second groups of size code bits that are stored in the memory means are equal.

14. A validation system as in claim 13 wherein:

a. a first parity bit and a second parity bit are sensed from the encoded medium and are stored in the memory means, and

b. means are coupled to the memory means and to the validation means that are constructed to couple a parity check signal to the validation means when the first and second parity bits and the data bits that are stored in the memory means correspond to a predetermined parity standard, the validation means being so constructed that it will not signify that a properly encoded medium has been correctly sensed until the parity check signal is generated.

15. An identification system comprising:

a. a data-encoded medium that includes a plurality of contiguous indicia in which each individual indicium is selected from a group of three or more different indicia, each one of said indicia having a different detectable characteristic, the characteristic of each individual indicium being different from the characteristic of its neighboring indicium, a datum value being defined by each transition from each indicium to the next contiguous indicium;

b. means to detect the characteristic of each indicium; and

c. decoding means coupled to said detecting means to remember the characteristics of an indicium until the characteristic of the next contiguous indicium is detected and to generate an encoded signal that is representative of the associated datum values of the particular characteristic relation of each detected contiguous two indicia.

16. The invention according to claim 15 in which said indicia can be detected in either a forward direction or a reverse direction and in which said encoded signal includes at least one direction datum value indicating the direction in which said indicia are being detected, said direction datum value being one value in the event said indicia are being detected in the forward direction and another value in the event said indicia are being detected in the reverse direction.

17. The invention according to claim 16 wherein said direction datum value causes a direction signal having a value reflecting the direction datum value to be provided, said direction signal indicating the direction in which said indicia are being detected.

18. The invention according to claim 17 wherein said system includes shift register means to which said encoded signal and said direction signal are applied, one value of said direction signal causing said shift register means to shift in one direction and another value of said direction signal causing said shift register means to shift in another direction.

19. The invention according to claim 18:

wherein said different characteristics of said indicia are first, second, and third different colors;

wherein said datum values are binary numbers, a first binary number being generated if the contiguous indicia are detected in the order of first-to-second, second-to-third, or third-to-first colors and a second binary number being generated if the contiguous indicia are detected in the order of third-to-second, second-to-first, or first-to-third colors; and

wherein one value of said direction signal causes each datum value in said encoded signal to be complemented.

20. The invention according to claim 19 wherein the first datum value generated when said indicia are detected in the forward direction results from contiguous first and subsequent second colors being detected, the last datum value generated when said indicia are detected in the forward direction results from contiguous third and subsequent first colors being detected, the first datum value generated when said indicia are detected in the reverse direction results from contiguous first and subsequent third colors being detected, and the last datum value generated when said indicia are detected in the reverse direction results from contiguous second and subsequent first colors being detected.

21. The invention according to claim 15:

wherein the last indicium detected is detected for a time substantially greater than the time at least one other of said indicia is detected; and

wherein said system further includes means to sense the time during which said last indicium is detected in relation to the time during which a selected indicium prior thereto is detected, and to generate a signal indicating that the final indicium has been detected.

22. The invention according to claim 15:

wherein said encoded signal includes a plurality of data datum values and a plurality of size code datum values, said size code datum values being encoded to be representative of the number of data datum values in said encoded signal; and

wherein said system further includes memory means for storing said data datum values and means for recognizing said size code datum values and for determining whether the number of stored data datum values properly corresponds to the code of said size code datum values.

23. The invention according to claim 22:

wherein said indicia can be detected in a forward direction or in a reverse direction; and

wherein said encoded signal has size code datum values preceding and following said data datum values, said indicia on said medium being so arranged that the size code datum values will be identical whether said indicia are detected in a forward direction or in a reverse direction.

24. The invention according to claim 23 wherein said means for recognizing said size code datum values recognizes the datum values stored in specified locations of said memory means.

25. The invention according to claim 24 wherein said specified portions of said memory locations store the datum values of the size code values following said data datum values.

26. The invention according to claim 25 wherein the code of said size code datum values preceding said data datum values is complementary in an opposite direction to the code of said size code datum values following said data datum values.

27. The invention according to claim 26 wherein the code of said size code datum values preceding said data datum is representative of the number of datum values of said data datum values.

28. The invention according to claim 15 wherein said decoding means includes means to provide an inhibit signal to inhibit the detection of any characteristic for a fixed time after a new characteristic is first detected.

29. The invention according to claim 15 wherein said inhibit signal providing means includes means to provide an indicium-detected signal when a new characteristic is first detected, means to delay said indicium-detected signal a fixed time, and means to inhibit said decoding means from detecting any characteristic for said fixed time.

30. The invention according to claim 15 wherein said encoded signal includes a plurality of data datum values and a plurality of other datum values, said other datum values including at least two datum values forming a parity code which is a function of the remaining datum values of said encoded signal.

31. The invention according to claim 30:

wherein said datum values are binary digits of "1" or "0;" and

wherein the code of said parity code represents the difference between the modulo 3 sum of the "1" binary digits of said remaining digits of said encoded signal and the modulo 3 sum of the "0" binary digits of said remaining digits of said encoded signal.

32. An identification system for detecting the binary code defined by a medium having a plurality of contiguous colored indicium thereon, the color of each of said indicia being selected from a group of at least three different colors, each of said indicia being positioned contiguous to an indicium of a different color therefrom, each binary digit of said code being defined by the transition from an indicium of one color to an indicium of another color, said system comprising:

optical means capable of being guided over a selected path traversing each of said indicia;

detection means to detect the color of each of said indicia along said selected path and to provide a signal indicative of the color of the then traversed one of said indicia; and

decoding means to which said detection means signal is applied for remembering the color indicated by the then occurring detection means signal until after the next detection means signal is provided, and to provide a binary digit as determined by the sequence of said then occurring detection means signal and said next detection means signal.

33. The invention according to claim 32:

wherein said binary code is divided into consecutive first, second, and third portions, said second portion having a plurality of data binary digits included therein, each of said first and third portions including at least one direction binary digit which is indicative of the direction in which said selected path is traversed, and a plurality of binary digits which are arranged in a code to represent the number of data binary digits in said second portion, at least one of said first and third portions including a plurality of parity binary digits which are arranged in a code to cause the direction binary digit in each of said first and third portions to be equal; and

wherein said identification system further includes memory means to store said binary code, logic means responsive to said plurality of size code binary digits in at least one of said first and third portions of said binary code which are stored in said memory means to determine whether the proper number of binary digits of said second portion of said binary code is being stored in said memory means, output shift register means responsive to said logic means determining that the proper number of binary digits of said second portion of said binary code are stored in said memory means for providing an output signal of a fixed sequential number of said binary bits, said output shift register means being responsive to said direction binary digit to shift in one direction for one value of said direction binary digit and to shift in another direction for the other value of said direction binary digit.

34. A record member for storing data in combination with means for reading said data comprising:

a record member having a plurality of at least three different indicia means with each one of said indicia means having detectable characteristics associated therewith, said indicia means being assigned to predetermined pair groupings so that each of said pair groupings contains two different indicia means, some of said pair groupings being assigned to a first group so that a transition from the first to the second indicia means of any pair grouping in the first group in a reading direction is indicative of a first datum, the remainder of said pair groupings being assigned to a second group so that a transition from the first to the second indicia means of any pair grouping in the second group in said reading direction is indicative of a second datum, said indicia means being selected from said pair groupings and arranged on said record medium in a predetermined reading order in a single track to provide said transitions corresponding to said first and second datum, each one of said indicia means being arranged on said record member in said predetermined reading order so that the next one of said indicia means in the direction of said reading order is always different from said one indicia means, each of said indicia means being capable of occurring at irregular intervals in said reading order;

detecting means for providing a signal indicative of the characteristic of the then detected indicia means; and

logic means, responsive to said detecting means signal, for providing a data signal indicative of the successive characteristic transition between each pair of indicia means.

35. The invention according to claim 34 wherein each of said indicia means is in the shape of a bar and said detectable characteristic of each bar is the color thereof.

36. The invention according to claim 35 wherein each bar is one of three colors, a transition from a bar of a first color to a bar of a second color, from a bar of said second color to a bar of said third color, and from a bar of said third color to a bar of said first color being indicative of the binary digit "1," and a transition from a bar of said third color to a bar of said second color, from a bar of said second color to a bar of said first color, and from a bar of said first color to a bar of said third color being indicative of the binary digit "0."

37. The invention according to claim 36 wherein one of said three colors is the background color of said record member having said color bars thereon.