Security Alarm Transmission Of Radio Frequency Coded Pulses

Abstract

A security alarm system wherein an alarm signal is sent by a transmitter which generates a radiofrequency carrier wave modulated by an audiofrequency signal which is further pulse code modulated. A receiver is provided which includes a tuned RF stage for selecting the transmitted signal, a detector and an audiofrequency filter for recovering the pulse modulated audiofrequency signal, and a pulse code demodulator for decoding the receiver pulses and supplying an actuating pulse to an alarm device.

Description

BACKGROUND OF THE INVENTION

This invention generally relates to the transmission and reception of coded radiofrequency signals and particularly concerns the utilization of such coded radiofrequency signals in security alarm systems.

Security guards and others responsible for the protection of large sums of money or other valuable goods are often required to raise an alarm with very little time to spare. In some cases, these guards risk being attacked or threatened before reaching a point from which an alarm can be raised. For example, when transferring money from a bank into a van, guards are very susceptible to surprise attacks. Ideally, the guards should be able to raise an alarm without attracting the attention of their would-be assailants.

One solution would be to provide the guards with a hidden transmitter capable of generating a coded radiofrequency signal to a receiver situated somewhere in an adjacent building. The receiver would need to be tightly locked or tuned to receive only the coded signals and neither the transmitter nor the receiver should be unduly complex. Moreover, to strengthen security, the receiver should preferably be readily adaptable to receive a number of different codes. The method of coding, therefore, appears as a critical factor in securing successful operation of a foolproof system.

Accordingly, it is an object of the present invention to provide a security alarm system utilizing coded radiofrequency signals.

It is another object of the present invention to provide a security alarm system that can be quickly and silently actuated.

It is a further object of the present invention to provide a security alarm system wherein the alarm transmitter can easily be hidden.

It is an additional object of the present invention to provide a security alarm system having foolproof operation.

It is another object of the present invention to provide a security alarm system of relatively simple construction.

It is a further object of the present invention to provide a security alarm system wherein the alarm receiver is capable of receiving a plurality of different coded alarm signals.

SUMMARY OF THE INVENTION

According to the present invention, the transmitter generates a radiofrequency signal modulated by an audiofrequency signal which is, in turn, pulse code modulated. The receiver includes a tuned radiofrequency stage, a detector and an audiofrequency filter to recover the pulse code modulated audio signal, and a pulse code demodulator which detects and subsequently reads the coded pulses to supply an actuating pulse or signal to an alarm device preferably after a predetermined number of correct code cycles have been received.

In a preferred from of the invention, the receiver has a number of sampling circuits triggered by the leading and trailing edges of the incoming code pulses. These pulses are in the form in which both marks and spaces may be of either short or long duration with a particular sequence of marks and spaces determining the code. The sampling circuits view the height of the waveform a predetermined interval after the leading or trailing edge of the pulse has been detected and in this way discover whether each pulse and each space is long or short. Each sampling circuit has an associated bistable circuit and, depending on the result of the sampling, i.e., depending on whether the preceding marks, or spaces are of long or short duration, the bistables will or will not be triggered from one state to another.

This technique overcomes the need for accurate synchronization since any errors are not cumulative, each mark or space being effectively self-sampling. A further bistable connected to the output of an earlier bistable acts as a shift register such that information regarding successive waveform periods can be stored simultaneously.

Selected outputs from the bistables corresponding to a particular code are gated to a triggering circuit for the alarm device. The gate opens once during each code cycle when the selected outputs are all set to a particular logical level. The triggering circuit preferably contains a delay circuit such that a predetermined number of these triggering pulses are necessary before the alarm device is finally actuated.

The audiofrequency modulating signal may be generated in the transmitter by a transistor multivibrator which is preferably protected against changes in ambient temperature and variations in supply voltage. This enables the system to be used in countries throughout the world under different climatic conditions.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood and objects other than those set forth above will become apparent when consideration is given to the following detailed description. Such description makes reference to the annexed drawings presenting preferred and illustrative embodiments of the invention, and wherein:

FIG. 1 is a block diagram of a transmitter for use in a system according to the invention;

FIG. 2 is a block diagram of a receiver for use with the transmitter of FIG. 1;

FIG. 3 shows the logic waveforms generated in the receiver of FIG. 2 when a particular code is received;

FIG. 4 is a complete circuit diagram of the transmitter of FIG. 1; and

FIG. 5 is a complete circuit diagram of the decoding circuit in the receiver of FIG. 2.

Like reference characters refer to like parts throughout the several FIGS. of the drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In FIG. 1 the four upper blocks represent a radiofrequency generator consisting of the crystal controlled oscillator, harmonic filter, driver stage and power amplifier. Radiation takes place from a self-contained loop antenna tuned to the carrier frequency.

The radiofrequency carrier is modulated to 100 percent by a composite signal derived from a precision multivibrator oscillating at 2.1 kc./sec. (the subcarrier generator) which is switched on an off for periods determined by the combination of a bistable and low-rate multivibrator. The detailed operation of the encoder is as follows.

Referring to FIGS. 1 and 4, the code generator basically consists of a multivibrator having transistors VT3, VT4, VT10, VT11, and a bistable with transistors VT1, VT2. By means of connections from points 1 and 2 to two of the points A, B, C, D a four state oscillator is arranged. Transistors VT3 and VT4 conduct alternately as in a conventional multivibrator. The period for which VT3 is cut off is determined by the value of the capacitor C6 and the value of the collector current of transistor VT11. Similarly, C1 and VT10 define the cutoff period of VT4. In this example, C1 and C6 are of the same nominal value. The collector currents of VT10 and VT11 are determined by their relative base potentials and the resistors R9 and R10. The values of R1, R4, R7, R5 are so chosen that the potential difference between A and the positive conductor is approximately twice that between D and the positive conductor. More exactly, the base-emitter voltage of the transistors VT10, VT11 is taken into account and the potentials at A, D, are designed to cause the ratio of maximum to minimum collector currents VT10, VT11 to be exactly 2: 1.

The values of R2, R3 are chosen so that either VT1 is cut off and VT2 saturated or vice versa. The circuit is switched from one state to the other at the instant that VT3 starts to conduct, and remains in each state for the duration of a complete cycle of oscillation by the multivibrator. Thus, a complete cycle of the bistable embraces two multivibrator cycles and hence four multivibrator periods. These periods will have "long " or "short " durations depending upon the particular base potentials of VT10 and VT11. As explained previously, a long duration is twice that of a short duration but this is merely a convention leading to less stringent demands on the decoding circuits.

As there are four multivibrator periods to one bistable cycle and each period may have one of two durations, the number of arrangements (i.e. codes) is 2.sup.4 or 16. Obviously, by increasing the number of bistables and suitable combining the signals, more complicated codes may be generated. Of the 16 codes generated by the system being described only 10 discrete codes may be distinguished, as shown in the table below.

TABLE OF CODES

CONVENTIONS

0 represents a short period

1 represents a long period

M represents a mark

S represents a space ##SPC1##

Like codes are linked by like letters.

Of these 10 codes, four, namely E. I. L, N, could be generated by the multivibrator acting on its own, and are not considered to be of sufficiently low probability to offer adequate protection against false operation of the alarm.

The remaining six usable codes namely F, G, H, J, K, and M, can each be generated by appropriate connections between points 1, 2, and A, B, C, D,. For example, code K requires that point 1 be connected to point A and point 2 to point B or C.

Additional reliability is obtained by causing VT3 to key an additional multivibrator consisting of VT5, VT6 via the switching transistor VT5A. This multivibrator oscillates at a frequency within the range 2--3 kc./sec., which is detected by a narrow band filter in the receiver decoder. This multivibrator is protected against changes in ambient temperature and variations in supply voltage by the diode D3 which appears in the supply lead to both collectors, while the timing resistors R15, R16 are returned directly to the supply conductor. If the base-emitter potential of a conducting transistor is designated Vbe, the potential across D3 designated Vd, and assuming that the current through D3 is constant and that the collector-emitter voltage of a saturated transistor is negligible compared to the supply voltage Vs, then it can be shown that t =

where t represents the timing of the multivibrator.

If, to a first approximation, Vd = Vbe then

Thus, the timing of the multivibrator is independent of the effects of temperature changes on Vbe of the transistors, and of supply voltage change so long as the voltage drops and temperature sensitivities of the base-emitter diodes and the compensation diode D3 are matched.

The waveform at VT6 collector is repeated by the emitter follower VT7 which drives the modulating transistor VT8 from collector to base, and this effectively limits the maximum rate of change of voltage of VT8 collector in order to minimize the radiation of unwanted sidebands. The radiofrequency driver transistor VT12 is allowed to conduct only when VT8 is in conduction, so that the power amplifier supplies energy to the radiating loop in accordance with the code.

Referring now to FIGS. 2 and 5, the receiver consists of a conventional superheterodyne with crystal stabilized local oscillators. The detected signal is fed to the decoder.

The subcarrier signal at a frequency of 2.1 kc./s. is isolated by means of the filter L,C2 which is energized by the gain stabilized transistor Q1. The bandwidth of the filter is fixed by R5. Transistor Q2 conducts current during the negative going half cycles of the waveform presented to its base. The current pulses charge the capacitor C4 which discharges via R7 and the filter R8, R9, C5 to the base of Q3. This circuit constitutes a peak detector and carrier filter, so that the signal presented to the trigger pair Q3, Q4 follows the code. The reconstituted code signal and its inverse appear at the collectors of Q4 and Q5 respectively. These signals are fed to the logic circuits which "read " the code.

In order to recognize one of the six codes and reject the remainder it is necessary to store the information relating to three successive points and use this information together with that of the fourth point to activate the alarm. In the interests of reliability and security, several sequential correct codes are detected before the alarm is activated.

The detection circuits are formed from five identifiable types:

a. "RS" type bistable

b. NOR Gate

c. triggered monostable

d. Schmitt trigger

e. inverter.

Considering, for example, the circuit of binary 1 in FIG. 5, the feedback and bias resistors R33, R36, R34, R35 are chosen to ensure that conduction in only one of the transistors Q11, Q12 is possible at any one time.

These states of conduction are stable and the circuit can be used to "store" one binary digit. The binary is switched from one state to the other by signals applied to the bases of Q11, Q12 via the diodes D4 and D5. Whether or not the diodes are able to pass signals on to the transistors is determined by the potential to which the cathodes of the diodes are "set." The "set" potentials are applied via the resistors R31, R38 and have the value of logical 1 or 0, i.e. at emitter or collector supply conductor potentials respectively. Similarly, the potentials applied via C17, C11 have the value of logical 1 and 0. When an abrupt transition occurs at Q4 collector, the voltage at D4 cathode changes comparatively slowly because of the presence of C17 and R31. However, when Q6 collector potential changes, D4 cathode potential follows instantaneously. Since the changes at Q4 and Q6 collector are of similar amplitude, it follows that only when Q4 collector is at logical 1 (i.e. at emitter conductor potential) and Q6 collector makes a negative going transition from logical 0 to logical 1 will D4 conduct and cause Q11 to be cut off, and Q12 to be forced into conduction. The logical function performed by R31, C17, D4 is that of an AND gate, i.e. only when the signal from Q4 is at logical 1 and a negative going transition occurs at Q6 collector will D4 conduct. The action of the gate formed by R38, C11, D5 is exactly the same. It should be noted that although the same transition signal from Q6 is applied to both C17 and C11, only one of the signals applied to R31, R38 will be at logical 1 because of the inverter Q5. The input signals to R31, R38 are conventionally the "set" or DC signals, and that applied via C17, C11 the AC signal.

The NOR gate consists of the circuit comprising transistor Q17, diodes D10--D13 inclusive and their associated components. The resistor chain R53, R54, R55 is so chosen that if the cathode potential of any diode is at logical 1, transistor Q17 is cut off, and its collector resides at logical 0. Thus, in order to enable conduction in Q17, all diode cathodes must be at logical 0.

The configuration of the monostable D1 in FIG. 5 is typical. The circuit has two states, one stable (the quiescent state), and one astable. The duration of the astable state is determined by the values of R21, C3. When a transition from 0 to 1 is applied via C6, Q6 is cut off and Q7 turned on. After the delay period, the states are reversed. The abrupt transition from 0 to 1 which occurs at Q6 collector at the end of the delay period is a suitable signal for gating the bistable to which it is connected.

The purpose of the SChmitt trigger at the beginning of the decoding circuit is twofold. Firstly to normalize input signals, and secondly to act as a voltage level detector. The signals formed by the action of the demodulator and subcarrier filter do not have fast or sharp edges and are not of uniform amplitude, but the Schmitt trigger operates on them to produce signals having the value of logical 0 or 1 and suitably fast transition between these levels. In FIG. 5, transistors Q3 and Q4 perform this function. The common emitter resistor R11 is sufficiently large to ensure that the circuit is bistable. In the absence of the subcarrier, Q3 is cut off, Q4 is in conduction and its collector resides at logical 1. Whenever the subcarrier is presented, the transistors change state abruptly due to the positive feedback and Q4 collector rests at logical 0. The input signal must have an amplitude greater than the threshold level (set by the value of R11) for the transition to occur, and use is made of this fact to enable the alarm relay to be operated at a suitable input voltage amplitude.

The action of the inverter is to provide logical 1 at its output whenever its input is at logical 0 and vice versa.

The operation of the decoding circuit is best illustrated with the waveform diagram of FIG. 3. Essentially the circuit would operate on the waveform corresponding to the code H as follows. The trailing edge of a mark appears as a o--1 transition at S1. This triggers the delay circuit D1 into its astable state for a predetermined interval following the trailing edge of the mark. If the subsequent space is short (in this case after a short mark), then the return pulse of D1 after the delay occurs during the following mark, i.e. when S1 is at 0. This triggers the bistable B1 from a 1 state to a 0 state. Hence, when the trailing edge of the next mark arrives and again triggers D1, the bistable B1 will only be able to change state if the succeeding space is long, i.e. if the return pulse from D1 occurs during the space, when S1 is at 1. If both spaces were long, B1 would sit continuously in the 1 state, and if both spaces were short, B1 would remain in the 0 state. The fact that, in this case, B1 is changing state during each cycle defines the code as having one long space and one short space.

Similarly, from the waveform diagrams it is clear that the leading edge of a mark appears as a 0--1 transition at S1. This triggers D2 which therefore views the mark length. In the same way as B1 defines the spaces, so B2 therefore defines the marks. TIn this example, since B2 is changing state during each cycle the code must also have one long mark and one short mark.

To completely define the code it therefore remains to determine the relative order of the marks and spaces within a code cycle. Firstly, therefore, the gate output is only made significant following the delay pulse from D1 by causing the delay pulse to trigger the delay circuit D3 when the gate output is a logical 1. Secondly, the third bistable B3 have its biasing inputs connected to the outputs of B2 and will register the state of B2 during the period preceding its last change of state at any one time during a cycle. In this example, the outputs S1, B2, B3 and B1 are connected to the gate input. With S1 connected, the gate output is only significant following a short space and the code is therefore restricted to one having at least one short space. B1 then further restricts the code to having one short space and one long space. Finally, B2 and B3 permit only those codes containing a long and a short mark but with the short mark immediately preceding the short space and, therefor, all codes except H are rejected. After Delay 5 has been triggered, it rests in its astable state for about three-quarters of one cycle time. Q13 collector potential thus goes to the collector supply conductor potential for a short time once per cycle. Each time this action occurs, an increment of charge is placed in C9 via R24. The voltage on C9 rises slowly until the trigger level or threshold of Schmitt 2 is reached, at which time the alarm relay is activated. The time constant B24, C9 is so chosen that about 10 complete cycles of the received code are required to be successfully detected before the alarm is activated. In practice, the "Bleep" transmitter must be activated for at least 0.5 second before an alarm will be given.

The transmitter should be small enough to fit in a pocket and is conveniently activated from a remote pushbutton which might, for example, take the form of a disguised wristwatch.

From the foregoing description, it should be readily apparent that the objects set forth at the outset of this specification have been successfully achieved.

Claims

We claim:

1. A security alarm system for transmitting and receiving coded signals, said system comprising:

A. radio transmitter means for generating an RF signal, said radio transmitter means being adapted to be carried camouflagedly by a person and including modulator means for modulating said RF signal with an audiofrequency signal itself modulated with a pulse code signal having short and long marks and spaces, said modulator means including:

1. A transistor multivibrator means for generating said audiofrequency signal, said transistor multivibrator means being connected by a supply conductor to a power supply with compensating diode means being inserted into said supply conductor for stabilizing the frequency of said transistor multivibrator means against changes in ambient temperature and power supply voltage;

2. A bistable multivibrator means and a slowly oscillating multivibrator means coupled together to generate said pulse code signal and connected to said transistor multivibrator means to switch the same in accordance with said pulse code signal; and

B. radio receiver means tuned to said RF signal for receiving the same, said radio receiver means including an intermediate-frequency stage, a detector means, an audiofrequency filter means, and pulse-decoding means, said pulse-decoding means including a plurality of delay circuit means controlled by changes in level of the received audiofrequency signal, and a plurality of bistable circuit means actuated by said delay circuit means for distinguishing between short and long intervals between the pulses and for detecting predetermined sequences of pulses, and an alarm triggering circuit means controlled by said decoding means, said alarm triggering circuit means being provided with a delay circuit means whereby an alarm device is actuated in response to the decoded signals.

2. A security alarm system as defined in claim 1, wherein said delay circuit means of said alarm triggering circuit means delays actuation of said alarm device until several sequential correct code are detected.

3. A security alarm system as defined in claim 1, wherein said receiver means further comprises means coupled therewith controlling said receiver such that the receiver only responds to a predetermined lowest input voltage, whereby no alarm triggering occurs in the event of a lower input voltage.

4. A security alarm system as defined in claim 3, wherein said receiver means includes inverter means for inverting incoming coded pulses, and wherein said delay circuit means responsive to changes in level of said audiofrequency signal comprises a first delay means triggered by the trailing edge of a mark, said first delay means being coupled to a first bistable circuit means for sampling the length of the spaces, and a second delay means triggered by the trailing edge of an inverted mark, said second delay means being coupled to a second bistable circuit means for sampling the length of the marks.

5. A security alarm system as defined in claim 4, wherein said receiver means includes a third bistable circuit means biased from the outputs of one of said first and second bistable circuit means respectively coupled to said first and second delay means, said third bistable circuit means storing information relating to the pulse immediately preceding the pulse which actuated said one of said first and second bistable circuit means.